A digital IC Random Number Generator with logic gates only

Güler, Ülkühan; Ergün, Salih; Dündar, Günhan

doi:10.1109/icecs.2010.5724498

Cited by 30 publications

(17 citation statements)

References 16 publications

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“…RNs have been used in many different areas like cryptography, simulation, modeling, test processes, lottery, games, genetic algorithms, secure communication, art, and music . Since the efficiency of the application results depends heavily on the quality of RNs, the production of RNs has a vital importance …”

Section: Basic Conceptsmentioning

confidence: 99%

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

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Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

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Section: Basic Conceptsmentioning

confidence: 99%

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

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“…In their method, the entropy source is designed by the Fibonacci Ring Oscillator (FIRO) and the Galois Ring Oscillator (GARO), which combines pseudo-randomness of the Linear Feedback Shift Register (LFSR) with the true randomness of the clock jitter. In 2010, based on Golic's method, Ülkühan et al [5] used seven entropy sources composed of 31 GAROs and 15 FIROs to achieve the highest random number output of 31.25 Mbit/s. The randomness of the random number generated by the above methods is mainly from true randomness of clock jitter and the pseudo-randomness introduced by LFSR method.…”

Section: Introductionmentioning

confidence: 99%

A true random number generator based on meta-stable state

Fan

Long

Luo

et al. 2018

IEICE Electron. Express

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This paper presents a ring oscillator structure which combines meta-stable states with Fibonacci ring oscillators (FIRO) and Galois ring oscillators (GAROs). Based on the new structure, a true random number generator (TRNG) of 64 bit was created. This new TRNG was verified by FPGA platform with Altera Cyclone IV series chips, and its output has attainted NIST SP800-22 certification. The testing demonstrates that the proposed meta-stable random number generators improve randomness over traditional methodologies.

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“…In a real circuit delays caused by inner connections cannot be ignored [36]. Moreover, propagation delays in all circuit paths and gates vary in time, because of shot noise, thermal noise and supply voltage instability [28], [41]. Taking into account these factors the more realistic formula for fH is the following [28], [39]:…”

Section: A a Combined Ro-based Random Bit Generatormentioning

confidence: 99%

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Łoza¹,

Matuszewski²,

Jessa³

2015

International Journal of Electronics and Telecommunications

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Abstract-Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components -the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies. analog random number generator in one microchip in order to be used in encryption/decryption process in dedicated solutions. Most of cryptographic systems are digital constructions. Therefore, it is expected that random number generators should be purely digital constructions, simply integrated in one chip. Nowadays there is a trend to find in digital circuits some behaviors or methods that will give possibility to produce random bit sequences "on demand", with high bit rate, without any possibility to having access to elements of these sequences. It is proposed to use generators with jitter, constructed by using reprogrammable digital circuits or constructions based on meta-stability [31], [32]. Because the latter phenomenon, although interesting, is rather impractical for producing random bits in contemporary FPGAs [33], the most significant are concepts using ring oscillators or Galois Ring Oscillators (GARO). In both approaches jitter is used for signal generation [27], [31]. Random bit sequence is obtained by sampling signal generated by RO or GARO with rectangular wave with lower frequency. To obtain unbiased sequence that pass all known statistical tests for random sequences, e.g. NIST 800-22 test suite, Diehard, TestU01 or UC1, we need to combine bit streams produced by many RObased random bit generators [34]- [39]. The ring oscillators must also have significantly different nominal frequencies to prevent the injection attack [40]. It forces to use delay lines built into FPGAs instead of inverters or latches [39]. KeywordsTo decrease the number of RO-based random bit generators necessary to pass all statistical tests, it is proposed in this paper to use SHA-256 hash function as post-processing. Both elements -RBG and SHA-256, were implemented in the same Virtex 5 FPGA (XL5VLX50T). Through experiments it has been shown that the minimal number of ROs that should be used for building a random ...

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A digital IC Random Number Generator with logic gates only

Cited by 30 publications

References 16 publications

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

A true random number generator based on meta-stable state

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

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