A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks

Vourkas, Ioannis; Abusleme, Angel; Ntinas, Vasileios; Sirakoulis, Georgios Ch.; Rubio, Antonio

doi:10.1109/ivsw.2016.7566607

Cited by 30 publications

(22 citation statements)

References 9 publications

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“…The programmable switches use Connection Boxes (CBs) to configure the connection from CLBs to the routing network, and use Switch Boxes (SBs) to configure the connections from different wire segments. There have been many studies [10,34,45,46,48,50] on using ReRAM to augment existing reconfigurable architectures. For example, ReRAM cells are used to replace SBs and CBs in FPGA [10] and to implement arbitrary logic function [50].…”

Section: Reconfigurable Architecturementioning

confidence: 99%

Fpsa

Zhang

Xie

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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Neural Network (NN) accelerators with emerging ReRAM (resistive random access memory) technologies have been investigated as one of the promising solutions to address the memory wall challenge, due to the unique capability of processing-in-memory within ReRAM-crossbar-based processing elements (PEs). However, the high efficiency and high density advantages of ReRAM have not been fully utilized due to the huge communication demands among PEs and the overhead of peripheral circuits. In this paper, we propose a full system stack solution, composed of a reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and its software system including neural synthesizer, temporal-to-spatial mapper, and placement & routing. We highly leverage the software system to make the hardware design compact and efficient. To satisfy the high-performance communication demand, we optimize it with a reconfigurable routing architecture and the placement & routing tool. To improve the computational density, we greatly simplify the PE circuit with the spiking

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Section: Reconfigurable Architecturementioning

confidence: 99%

Fpsa

Zhang

Xie

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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“…Equation (1) reflects the inputs of the block, the initial memristance value (RINIT), which is loaded when reset = '1', and two 2-bit flag signals to denote whether its terminals are properly connected, i.e., whether the applied voltage is valid or has been left floating (the need for two bits instead of one is explained in Section IV). Unlike in [32], in this version of the simulator design, the output signal in most cases concerns the memductance G = R -1 because using G instead of R enables a simplified circuit design, lower HW resource requirements, and greater computational precision, as shown in the following sections. The model-specific parameters α, b, vT, RMIN, and RMAX are defined as internal constants (stored in memory) since we assume they are device/module-specific.…”

Section: A the Behavioral Memristor Modelmentioning

confidence: 99%

“…Moreover, the fixed amplitude of the action pulses is not defined inside the neurons but rather is set externally and thus applied directly to the corresponding terminal of every memristor, as shown below. Unlike in our previous work [32], here we included a second neuron output VSIGN indicating whether the back-propagating pulses have a negative sign. As we will show below in our ANN examples, unlike in [31], [32], this important added property makes it possible both to increase and decrease the synaptic weights through the simplified STDP scheme implemented here, previously proposed in [38] (although action potentials resembling more the true spike waveforms found in biological neural systems, as presented in [36], [39], [40], could be implemented as well by more HW resources).…”

Section: A Circuit Implementationmentioning

confidence: 99%

“…According to [30], the required features for a memristor emulator are: i) a wide memristance range; ii) nonvolatility; iii) initial state configurability; iv) floating operation; v) operability for high-frequency and continuous input signals; and vi) support interconnection with other components. Taking these six electrical requirements into account, in this paper we build upon our previous work in [32] and develop a fully digital memristor hardware simulator based on a behavioral model of voltage-controlled threshold-type bipolar memristors [27]. The presented electronic module constitutes the core of a digital memristor emulator, which further requires interface circuitry to permit connection to external circuits as a two terminal element, such as in [27], [31].…”

Section: Introductionmentioning

confidence: 99%

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Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator

Ntinas

Vourkas

Abusleme

et al. 2018

IEEE Trans. Neural Netw. Learning Syst.

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This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

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“…The drawbacks of analog emulators are the limitations on power supply voltages, sensitivity to process variations and temperature, number of elements and hardware implementation. In addition, the capacitor needed in the memristor analog model requires a large on-chip area to store the system state [17], [18]. On the other hand, digital emulator does not demand any analog components, where the system's states are stored in a register.…”

Section: Introductionmentioning

confidence: 99%

Digital Emulation of a Versatile Memristor With Speech Encryption Application

et al. 2019

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Memristor characteristics such as nonlinear dynamics, state retention and accumulation are useful for many applications. FPGA implementation of memristor-based systems and algorithms provides fast development and verification platform. In this work, we first propose a versatile digital memristor emulator that exhibits either continuous or discrete behaviors, similar to valence change memories (VCM) and the electrochemical metallization memories. Secondly, the proposed memristor emulator is used to design a chaotic generator circuit utilizing the memristor's nonlinearity. Finally, the chaotic system is used to design a speech encryption engine to demonstrate its capabilities. The memristor emulator, chaotic generator, and the encryption system were implemented on Nexys 4 Artix-7 FPGA XC7A100T. The implementation results show an efficiency in throughput and hardware resources utilization compared to the previous works. In addition, the encryption system results show good performance against several perceptual, statistical attacks in addition to resistance to security attacks tests including differential attacks, NIST tests, key space analysis, mean square error (MSE), correlation, histogram and spectrogram.

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A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks

Cited by 30 publications

References 9 publications

Fpsa

Fpsa

Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator

Digital Emulation of a Versatile Memristor With Speech Encryption Application

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