A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

Abstract

Abstract-We design and implement a key building block of a scalable neuromorphic architecture capable of running spiking neural networks in compact and low-power hardware. Our innovation is a configurable neurosynaptic core that combines 256 integrate-and-fire neurons, 1024 input axons, and 1024x256 synapses in 4.2mm 2 of silicon using a 45nm SOI process. We are able to achieve ultra-low energy consumption 1) at the circuit-level by using an asynchronous design where circuits only switch while performing neural updates; 2) at the core-level by implementing a 256 neural fanout in a single operation using a crossbar memory; and 3) at the architecturelevel by restricting core-to-core communication to spike events, which occur relatively sparsely in time. Our implementation is purely digital, resulting in reliable and deterministic operation that achieves for the first time one-to-one correspondence with a software simulator. At 45pJ per spike, our core is readily scalable and provides a platform for implementing a wide array of real-time computations. As an example, we demonstrate a sound localization system using coincidence-detecting neurons.

Neural spiking dynamics in asynchronous digital circuits

“…Our design is well suited for architectures that exclusively use local on-chip memory, such as the recently implemented neurosynaptic core [17,19]. In the neurosynaptic core architecture, individual neurons store their parameters in local registers and a crossbar memory local to a neuron core implement large synaptic fanout efficiently.…”

“…The period of the update signal provides an absolute bound within which all the communication and computation in the system has to take place. With the use of synchronization circuits, this kind of design can create a one-to-one correspondence between hardware operation and software simulation [17,19].…”

“…Fortunately, neuron activity is measured in the Hz range, whereas ASIC wire bandwidth can reach hundreds of MHz to several GHz. Thus, most custom-ASIC neuromorphic systems [19,23,24] time multiplex wire usage to implement the connections of a group of neurons, encapsulated in neural cores.…”

“…Neuron models can be implemented using compact and energy-efficient circuits [2], memories storing configuration parameters can be tightly coupled to computing datapaths [17], routing fabrics can be tailor-made for spike-based communications [18], and synchronization methods can be deployed to maintain hardware correspondence with software [19].…”

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

“…However, to meet the requirement of real-time interaction with the environment, some of the recently proposed VLSI design solutions that operate only on "accelerated time" scales (i.e., in which unit of real time is "simulated" in hardware two or three orders of magnitude faster), are not suitable [7], [8]. Similarly, neural VLSI solutions that focus on large-scale systems simulations are not ideal, as they compromise the low-power or compactness requirements [9]- [12]. In this paper we propose a compact full-custom VLSI device that comprises low-power sub-threshold analog circuits and asynchronous digital circuits to implement networks of spiking neurons with programmable synaptic weights [13], [14].…”