A Digital-Pixel-Sensor-Based Global Feature Extraction Processor for Real-Time Object Recognition

Abstract

In this paper, a global feature extraction very large scale integration (VLSI) architecture for real-time object recognition is presented. To minimize the latency between capturing images and final recognition, the image sensor and feature extraction circuits are integrated on the same chip. The digital pixel sensor (DPS) configuration has been used because of its intrinsic compatibility with digital processing circuits. A block-readout architecture developed for DPS has been adopted for the massively parallel processing of image data. As a result, the directional edge filtering at each pixel site for local feature extraction is performed in a line-parallel manner. To eliminate trivial local features, the rank-order filter algorithm has been adapted for the processing and implemented in an efficient global feature extraction circuitry that can retain any given number of relatively more significant features in an image as essential features. This is accomplished in only 11 cycles. A proof-of-concept chip was designed in a 0.18 mm five-metal complementary metal-oxide-semiconductor (CMOS) technology, and the function of this VLSI processor was verified by circuit simulation.

A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture

“…1 shows the MSEM generation. First, four significant edge maps (SEMs) are generated from an input image based on the four-directional edge filtering (horizontal, + 45°, vertical, and −45°), as in [52]. Then, the four SEMs are merged into a single edge map by taking logical OR, which we call an MSEM.…”

“…3) using shift register arrays and broadcast to all groups of LFE circuits. This LFE architecture was first implemented in a 0.18-μm technology in [52] for still image recognition with a 68 × 68 DPS array. The following MFE function has been developed for the first time in this paper, and all digital circuits are implemented in a 65-nm technology.…”

“…Then, the Thresholding Mode signal selects the output signal from the binary sorting circuits to be transferred to the full parallel adder. According to the rank-order filtering structure, the MSEM can be extracted efficiently [52]. After the binary sorting, the MSEM datum of each pixel site is always preserved in the Flag Reg.…”

“…As a result, high-speed image processing systems have been realized. For example, a still image recognition system with a processing time of only 906 μs per frame is reported in [57] using the processor in [52]. Besides the still image analysis, a directional-edge-based object tracking algorithm is also proposed in [58] with its FPGA implementation in [59], in which a speed of 150 frames/s was experimentally demonstrated, and a speed of 900 frames/s was expected if the algorithm was directly implemented on VLSI with an on-chip image sensor.…”

VLSI processor with a configurable processing element array for balanced feature extraction in high-resolution images

“…[22][23][24][25] Processors for the thresholding were also developed. [26][27][28] The VLSI processor in Ref. 26 performs the thresholding by assigning the edge flag for each pixel on the basis of the relative significance of its gradients in the 5 © 5 neighboring pixel site (the fixed local region).…”