A digital signal processing based bit synchronizer and novel hardware efficient lock detector circuit for bi-phase data for Chandrayaan-1 mission

Sharma, Shubham; Kulkarni, Sunil; Pujari, V. Kumar; Lakshimnarsimhan, P.

doi:10.1109/tencon.2008.4766754

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Related Work Section: Unwrapping the Phase Obtained Fro2

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2012

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“…Finally the unwrapped phase is differentiated to recover the data. This bit synchronizer also refers as Data transition tracking loop (DTTL) [4]. It operates in a closed loop and combines the operations of bit detection and bit synchronization.…”

Section: Related Work Section: Unwrapping the Phase Obtained Fromentioning

confidence: 99%

“…The filtered output of the multiplier is used to drive the Numerically Controlled Oscillator (NCO) and timing circuit is designed to control the integrate-and-dump operations as shown in figure 6. It is possible to improve noise performance while SNR is above threshold by narrowing the mid phase integration window to T/4 [4]. The bit synchronizer can be modeled as a PLL with feedback system as shown in figure 7.…”

Section: Related Work Section: Unwrapping the Phase Obtained Fromentioning

confidence: 99%

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