A digital switching scheme to reduce DAC glitches using code-dependent randomization

Chacon, Oscar Morales; Wikner, J. Jacob; Alvandpour, Atila; Siek, Liter

doi:10.1109/norcas53631.2021.9599651

Cited by 2 publications

(3 citation statements)

References 11 publications

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“…Furthermore, considering the area versus matching trade-off, this solution enables an improvement by a factor √ 2 of the matching performance of the DAC for the same area of the unit current source. Finally, a conventional switching scheme has been adopted since the implementation of code-dependent randomization techniques to suppress the deterministic gradient error of the DAC would have had a negligible impact on the system performance [33], [34], [35].…”

Section: A Bjt Corementioning

confidence: 99%

An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS

Aprile,

Folz,

Gardino

et al. 2024

IEEE J. Solid-State Circuits

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This article presents a bipolar junction transistor (BJT)-based smart temperature sensor employing a noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC). This approach, never explored before within a temperature sensing system, was chosen to exploit the low energy/conversion benefit peculiar to SAR-based solutions while overcoming their quantization-dominated resolution with an error-feedback technique. In addition, the system features a complete current-mode architecture enabling op-amp less signal processing and resulting in a highly compact design. Developed and fabricated in a standard 180-nm CMOS process, the sensor exhibits an active area of 0.057 mm 2 and draws a 34-µA total current from a 1.8-V supply. Experimental results in the −50 °C to 110 °C sensing range demonstrate a 92-mK resolution in a conversion time of 80 µs.

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Section: A Bjt Corementioning

confidence: 99%

An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS

Aprile,

Folz,

Gardino

et al. 2024

IEEE J. Solid-State Circuits

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show abstract

“…However, it does not avoid complementary bit transitions that lead to DAC glitches. Both implementations require a register to keep the previous state, thus adding extra clock load that [67] increases the power consumption.…”

Section: Enhancement Techniquesmentioning

confidence: 99%

“…On the other hand, an switching block to reduce the DAC glitches, switching activity and generate code-dependent randomization with no added clock load has been proposed and presented in Fig. 3.29 [67]. The input-output mapping state is changed once a complementary switching transition is identified by the decoding logic.…”

Section: Enhancement Techniquesmentioning

confidence: 99%

Studies on the performance bounds and design of current-steering DACs

Chacon¹

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It has been a journey since I started off my PhD studies at Linkoping university back in 2017. During this time, I have had the opportunity to meet and work with people who have gave me inspiration, advise, encouragement and support along the way, and for those I would like to give my deepest and sincere gratitude • My supervisors at LiU and NTU. Prof Jacob Wikner for his guidance and support that has been key to carry on with the research studies and from whom I have learned a lot. Prof Atila Alvandapour for his guidance, unconditional support and the opportunity to start this journey. Prof Liter Siek for the opportunity to be part of NTU and his always advice and support regardless time and distance. • Prof Emeritus Christer Svensson who has been very inspirational and always willing to teach and be part of technical discussions. • Prof Ted Johansson who I started my PhD studies with and from who I always found advice, support and interesting conversations. • Past and present members in the Integrated Circuits and Systems (EKS) group at Linkoping university for all the discussions and collaboration in teaching, research or other activities.

show abstract

A digital switching scheme to reduce DAC glitches using code-dependent randomization

Cited by 2 publications

References 11 publications

An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS

An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS

Studies on the performance bounds and design of current-steering DACs

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