Ph~ne: (716) 477-8386 Fax: (716) 4774947 A VLSI chip that can perform either 3x3 matrix multiplication or 3x3 digital convolution has been developed. Built m self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chii is designed in a 2 pm CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz malting it suitable for real-time video and image prooessing applications.
l "With the advancement of VLSI processing and design techniques, one or more specific algorithms can be realized in a high-performance compact processor IC.These new processors solve the VO and computational bottlenecks associated with image processing [l]. The vector multiplication and convolution chip (VMCC) is a digital processor capable of 3x3 matrix multiplication or two dimensional canvolution.In a digital copier, the 3-channel color data comes from a scanner. The data arc formacted in the RGB color space. In order to have high quality copy output, an unsharp masking operation needs to be applied to the image to enhance the sharpness. To do the unshaxp masking, the data need to be converted into chrominance and luminllnce cbannels. The color space conversion needs a 3x3 matrix multiplication operation. After the conversion, a convolution Operation is applied to the is a solution to both functions. luminance channel to enhance the sharpness. Ihe VMCC In the color nndition of hardcopy prints from electronic cameras, the RGB signals captured by the camera need to be linearly matrixed and processed for color sensitivity c o d o n using 3x3 matrices [2].In image processing, noise reduction, feature extraction, image enhancement and restoration can be performed by linear filtck, i.e., 3x3 convolven. By providing different kernels to a convolver, it is capable of functioning as various filters for image processing. The VMCC is a single chip solution for all these functions.The functional block diagram of the VMCC is shown in Fig. 1. Each rectangle represents an n-bit register, which latches independent results in the pipelined operation. The V shaped block is a 240-1 multiplexer, the symbol B) is a multiplier, and the symbol represents an adder. For the 3x3 matrix multiplication operation, the input signals IN-2, IN-1, and IN-0 correspond to 3 attributes of the same pixel e.g., R, G, B, and are applied to each channel of three multipliers and two adders that perform vector multiplication and addition (VMA). For the 3x3 convolution operation it is assumed that the inputs correspond to pixels from three lines of image data. The outputs of the VMA channels are summed to form the convolution output. Real-time operation is achieved with a latency of six clock cycles. The operating speed of 14.3 MHz is suitable for real-time NTSC video processing.The coefficients C22, C21, C20, C12, C11, C10, CO2, Col, COO can be loaded either bit-parallel byte serial or bit-parallel byte parallel through the nine static registers which can be cofligured for the above two mode...
