A digitally programmable delay element: design and analysis

This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ∼ 1.1 V and 20 mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45 nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.

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“…One of the popular approaches to implement a delay cell is to use currentstarved inverters [11] shown in Fig. 2-a.…”

Section: The Controllable Delay Element (Cde)mentioning

confidence: 99%

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

Ryu

Kim

2013

IEICE Electron. Express

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“…The highlighted basic pulse generator (BPG) and time delay block are for generating the basic pulse p(t) and time delay T d in (3), respectively. The time delay block can be realized by CMOS time delay cells, which can provide fine delay time in the order of hundreds of ps [12]. The BPG can be implemented using any CMOSfriendly UWB pulse generator, which can be easily found in publications.…”

Section: Cmos Implementation and Experimentsmentioning

confidence: 99%

Frequency notching applicable to CMOS implementation of WLAN compatible IR-UWB pulse generators

Shen

Mikkelsen

Jiang

et al. 2012

2012 IEEE International Conference on Ultra-Wideband

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Abstract-Due to overlapping frequency bands, IEEE 802.11a WLAN and Ultra Wide-Band systems potentially suffer from mutual interference problems. This paper proposes a method for inserting frequency notches into the IR-UWB power spectrum to ensure compatibility with WLAN systems. In contrast to conventional approaches where complicated waveform equations are used, the proposed method uses a dual-pulse frequency notching approach to achieve frequency suppression in selected bands. The proposed method offers a solution that is generically applicable to UWB pulse generators using different pulse waveforms. In addition the method can be easily implemented. A prototype UWB pulse generator designed using the proposed method has been fabricated in a standard 0.18 µm CMOS process for verification, and satisfactory results are found.

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“…This suggests that less performance penalty would be introduced if the delays padded on adversary paths only delay the required unidirectional transition. This could be achieved by using the current-starved delay [65] [66]. Two examples of the current-starved delay are presented in Figure 7.4.…”

Section: Decomposition Of Or-causalitymentioning

confidence: 99%

Redressing timing issues for speed-independent circuits in deep submicron age

Mak

Yakovlev

2011

2011 Design, Automation &Amp; Test in Europe

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Signature from head of PhD committee:ii )>IJH=?J With continued advancement in semiconductor manufacturing technologies, process variations become more and more severe. These variations not only impair circuit performance but may also cause potential hazards in integrated circuits (IC). Asynchronous IC design, which does not rely on the use of an explicit clock, is more robust to process variations compared to synchronous design and is suggested to be a promising design approach in deep-submicron age, especially for low-power or harsh environment applications.However, the correctness of asynchronous circuits is also becoming challenged by the shrinking technology. The increased wire delays compared to gate delays and threshold variations could bring glitches into the circuit.This work proposes a method to generate a set of sucient timing constraints for a given speed-independent circuit to work correctly when the isochronic fork timing assumption is lifted into a weaker timing assumption. The complexity of the entire process is polynomial to the number of gates. The generated timing constraints are relative orderings between the transition events at the input of each gate and the circuit is guaranteed to work correctly by fullling these constraints under the timing assumption.The benchmarks show that both the number of total constraints and the constraints that are only needed to eliminate strong adversary paths are reduced by around 40% compared to those suggested in the current literature, thus claiming the weakest formally proved conditions. I would like to thank Dr. Terrence Mak for his education on research in both technique aspect and non-technique aspect.

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A digitally programmable delay element: design and analysis

Cited by 139 publications

References 9 publications

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

A high resolution and high linearity 45nm CMOS fully digital voltage sensor for low power applications

Frequency notching applicable to CMOS implementation of WLAN compatible IR-UWB pulse generators

Redressing timing issues for speed-independent circuits in deep submicron age

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