An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.Introduction: At present, to achieve fast and low-power read operation, small-swing bitlines and clocked sense amplifiers (SAs) are utilised in SRAM designs. For reliable operation at high speed, the sense amplifier enable (SAE) signal must track the small-swing bitline delay across global and local process, voltage and temperature (PVT) variations [1]. If the SAE arrives early before the bitline voltage difference reaches the SA offset, a read failure may happen. By contrast, unnecessary access time and power consumption will be increased [2][3][4][5]. Generally, the SAE signal is self-timed using the replica bitline (RBL) technique, since it tracks bitline delay better than simple inverter chains [2]. To suppress the timing variation of SAE, a configurable RBL technique by selecting low-variation replica cells (RCs) to drive the RBL is proposed in [1]. Unfortunately, it costs many additional postsilicon tests. A multi-stage RBL technique, with an inverter inserted in each of the two stages, is proposed in [3]. However, it is considered to be unsuitable for low-voltage operations [4]. In [4], with the usage of K times RCs in a replica column and timing multiplier circuit (TMC), a digitised RBL delay (digitised-RBD) technique has been developed. The disadvantage of this scheme is that the quantisation noise as well as the area of the TMC becomes larger as the count of RCs increases [5]. With the RBL segmented into M stages and K times RCs used in each stage, another technique called multiple-stage parallel RBL delay addition is proposed in [5]. The target SAE timing is generated by the timing addition circuit (TAC) constituted of an M × K stages digital delay circuit. Also, the quantisation noise as well as the area of the TAC becomes larger as M and K increase. Considering area efficiency, a novel dual RBL delay (dual-RBD) technique is proposed in [6], which makes the best use of the non-discharged bitline in the conventional RBL technique to reduce the standard deviation of the SAE timing to the conventional RBL's 1/ 2 √ . Nevertheless, because of the doubled capacitance of the RBL, extra access time will be incurred during the pre-charging stage.In this Letter, an efficient RBL technique is presented, which simultaneously utilises four times RCs and the non-discharged bitline of the conventional RBL scheme. Theoretically, the standard deviation of SAE timing can be reduced by 50% compared with that in conventional RBL. In this case, compared with the conventional RBL and dual-RBD ...