2010
DOI: 10.1109/tcsi.2009.2027645
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A Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method

Abstract: Abstract-The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the QuasiLinear interpolation (QLIP) method. The four-segment QLIP is utilized to realize a DDFS with a spurious free dynamic range (SFDR) of 63.2dBc. The DDFS chip featuring a 5-stage pipeline is implemented in TSMC 0.13μm technology. The chip occupies 9874μm 2 , consumes 8.2μW/MHz, and runs at 1GHz clock rate.

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Cited by 34 publications
(11 citation statements)
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“…To provide a redundant CORDIC applicable to all modes and coordinate system, this paper propose the following enhancement: (1) we extend the double rotation technique to work in hyperbolic coordinate (2) in order to decide the rotation direction for vector mode, we develop a scheme to estimate the angle of vector from its redundant representation (3) we show that the calculation of rotation direction and next vector components can be parallelized to achieve shorter cycle time.…”
Section: Proposed Algorithm and Implementationmentioning
confidence: 99%
See 1 more Smart Citation
“…To provide a redundant CORDIC applicable to all modes and coordinate system, this paper propose the following enhancement: (1) we extend the double rotation technique to work in hyperbolic coordinate (2) in order to decide the rotation direction for vector mode, we develop a scheme to estimate the angle of vector from its redundant representation (3) we show that the calculation of rotation direction and next vector components can be parallelized to achieve shorter cycle time.…”
Section: Proposed Algorithm and Implementationmentioning
confidence: 99%
“…Direct digital frequency synthesizer [1] [2], Phong shaders [3] [4], geometrical transformation [5] [6], and N-body simulation [7] are some examples. Although software implementations based on polynomial approximation are available and easy to implement, they usually become the bottle neck for computation intense and real-time applications like 3D graphics processing and robotics.…”
mentioning
confidence: 99%
“…The II-bit frequency control word (FCW) fed to the accumulator determines the phase step and the frequency resolution. In the proposed architecture, the phase accumulator output is quantized according to (7). After the phase accumulator output reaches (rr/4)*2 N , the comparator resets the accumulator content to O.…”
Section: Digital Realiza Nonmentioning
confidence: 99%
“…This method has several drawbacks including a large chip area and high power consumption [3]. There are various algorithms for DDFS design, including methods of table lookup, CORDIC algorithm [4], polynomial approximation [5] - [7]. The CORDIC DDFS algorithms have the trouble of slow sequential convergence operation.…”
Section: Introductionmentioning
confidence: 99%
“…The PSM could be as simple as a lookup table or as complex as a Coordinate Rotation Digital Computer (CORDIC) system [2]. Piecewise polynomial interpolation methods are also used to approximate the sine signal by polynomials [3]- [6]. In this method, the first quadrant of the sinusoid is divided into s = 2 u segments, and each segment is approximated by Manuscript a polynomial.…”
Section: Introductionmentioning
confidence: 99%