A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling

Lehne, Mark; Raman, Sanjay

doi:10.1109/tcsi.2010.2050232

Cited by 14 publications

(5 citation statements)

References 45 publications

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“…where X(k) and X(N − k) are obtained from (2). At the receiver, the received signal in (5) is passed through the DHT, and the frequency-domain received symbol at the kth subcarrier is produced as shown below:…”

Section: System Modelmentioning

confidence: 99%

“…In conventional OFDM systems, modulation, and demodulation of the orthogonal subcarriers are carried out using inverse discrete Fourier transform (IDFT) and discrete Fourier transform (DFT), respectively [1]. These operations are made fast and affordable due to the existence of many fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) algorithms as well as advances in field-programmable gate arrays (FPGA) [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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Frequency-domain subcarrier diversity receiver for discrete Hartley transform OFDM systems

Al-Gharabally

Almutairi

2019

J Wireless Com Network

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In recent years, there has been an increasing interest in the use of the discrete Hartley transform (DHT) for orthogonal frequency-division multiplexing (OFDM). Previous studies have not reported an improvement in bit error rate (BER) when using a DHT-based OFDM without substantial complexity increase due to the fact that the DHT cannot diagonalize a circulant channel matrix but rather produces a unique structured matrix that has only a main diagonal and anti-diagonal. In this paper, the coupling between symmetric carriers is exploited by introducing a frequency-domain subcarrier diversity receiver for DHT-based OFDM systems. The proposed simple receiver structure takes advantage of the coupling to enhance the BER performance of the DHT-OFDM system by increasing the diversity gain between subcarriers. A detailed statistical and performance analysis of the system is presented, in which closed-form expressions of the average BER were derived. The proposed system performance was compared to the conventional discrete Fourier transform OFDM (DFT-OFDM), the generalized DHT-OFDM, and the DHT-precoded OFDM systems in terms of average BER and peak-to-average power ratio (PAPR). The proposed DHT-OFDM system outperforms the generalized DHT-OFDM system by 12 dB and outperforms the conventional DFT-OFDM and the DHT-precoded OFDM systems by 17 dB at an average BER of 10 −5. In terms of PAPR, the proposed DHT-OFDM system suffers from an approximately 5.5, 2, and 1 dB increase in PAPR when compared to the DHT-precoded OFDM, the conventional DFT-OFDM, and the generalized DHT-OFDM systems, respectively.

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Section: System Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Frequency-domain subcarrier diversity receiver for discrete Hartley transform OFDM systems

Al-Gharabally

Almutairi

2019

J Wireless Com Network

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“…The proper architecture and data flow need to be explored for real-time application. The FFT module, which is a widely-used signal processing tool, is used to perform the signal analysis [7]. At the same time, maintaining a low false alarm probability is an essential goal in the FMCW radar system.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

Guo

Zhao

et al. 2023

IEEE Access

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In this paper, a pipelined frequency-modulated continuous-wave (FMCW) radar baseband processor applied to real-time applications is proposed and implemented in 40-nm CMOS technology. The FMCW radar signal processing time is analyzed according to the system specifications. On the basis of the theoretical analysis and systematic considerations, a pipelined baseband architecture with internal singleport static random access memory (SRAM) is employed. The baseband processor is mainly composed of two-dimensional fast Fourier transform (2D-FFT), two-dimensional constant false alarm rate (2D-CFAR), digital beam-forming (DBF), and memory control modules. The 2D-FFT module is structured with a pipelined scheme and avoids the waste of data transferring time between modules. The 2D-CFAR module is programmable for different applications. The designed address control is proposed to depose the edge cells. The processor occupies a core chip area of 3.353 mm ×3.353 mm and has been tested on the personal computer (PC) and field programmable gate array (FPGA) platform. The power consumption and processing time are also analyzed and compared with other works. The processor consumes 55.65 mW, including SRAMs. The processing time is 12.67 ms with the maximum window size and 256 targets when operating at 125 MHz. This time is estimated based on the assumption that each chirp lasts for 0.04096 ms, and data input takes 10.48 ms. Within this period, the range FFT is completed. The Doppler FFT, 2D-CFAR with the maximum window size, and DBF with 256 targets require 0.80 ms, 1.16 ms, and 0.23 ms respectively.

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“…Fast Fourier Transform (FFT) algorithm is widely applied in many applications, including wireless communication [1] [2], image processing [3], correlation, linear filtering and other spectrum analysis. For the case of N-point radix-2 FFT where 2 v N = , one popular algorithm decimates the input sequence by a factor of 2 and repeats this decimation recursively until only two-point Discrete Fourier Transform (DFT) is performed in the first stage [4].…”

Section: Introductionmentioning

confidence: 99%

New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT

Chen

Ding

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a new design algorithm is proposed to synthesize low complexity twiddle factor multipliers in radix-2 FFT. A prudently defined cost function has been proposed as a measure of hardware complexity when generating trigonometric expressions for the complex multiplier coefficients. The selected trigonometric expressions of the coefficients lead to cost efficient implementation of twiddle factor multipliers by maximizing the sharing of both trigonometric expressions and weight-two common subexpressions in the coefficients. The effectiveness of the proposed design algorithm are demonstrated using two design examples where the proposed solution saves up to 31% of arithmetic operator and multiplexer costs over other existing methods.I.

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A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling

Cited by 14 publications

References 45 publications

Frequency-domain subcarrier diversity receiver for discrete Hartley transform OFDM systems

Frequency-domain subcarrier diversity receiver for discrete Hartley transform OFDM systems

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT

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