A distributed and topology-agnostic approach for on-line NoC testing

Kakoee, Mohammad Reza; Bertacco, Valeria; Benini, Luca

doi:10.1145/1999946.1999965

Cited by 51 publications

(13 citation statements)

References 22 publications

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“…Designing and defending against HTs in a chip has been a hot research topic [2,3,4,1,5,6]. Various HTs and countermeasures have been proposed [2,7,8,9,10,11,12]. A typical HT is made of the trigger, the Trojan circuit and the payload [1].…”

Section: Hardware Trojansmentioning

confidence: 99%

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

Zhang

Wang

Jiang

et al. 2018

Journal of Systems Architecture

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There are ample opportunities at both design and manufacturing phases to meddle in a many-core chip system, especially its underlining communication fabric, known as the networks-on-chip (NoC), through the inclusion of malicious hardware Trojans (HT). In this paper, we focus on studying two specific HT-assisted Denial-of-Service (DoS) attacks, namely the sinkhole and blackhole attacks, that directly target the NoC of a many-core chip. As of the blackhole attacks, those intermediate routers with inserted HTs can stop forwarding data packets/flits towards the packets' destination; instead, packets are either dropped from the network or diverted to some other malicious nodes. Sinkhole attacks, which exhibit similar attack effects as blackhole attacks, can occur when the NoC supports adaptive routing. In this case, a malicious node actively solicits packets from its neighbor nodes by pretending to have sufficient free buffer slots. Effects and efficiencies of both sinkhole and blackhole DoS attacks are modeled and quantified in this paper, and a few factors that influence attack effects are found to be critical. Through fine-tuning of these parameters, both attacks are shown to cause more damages to the NoC, measured as over 30% increase in packet loss rate. Even with current detection and defense methods in place, the packet loss rate is still remarkably high, suggesting the need of new and more effective detection and defense methods against the enhanced blackhole and sinkhole attacks as described in the paper.

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Section: Hardware Trojansmentioning

confidence: 99%

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

Zhang

Wang

Jiang

et al. 2018

Journal of Systems Architecture

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“…Similar to scouting packets, a common method used for fault detection is the broadcasting of test vectors, either during boot-up [Strano et al 2011;Hosseinabady et al 2007] or at runtime. In order to mitigate the performance degradation caused by testing interruptions, token-based mechanisms have been explored [Kakoee et al 2011a[Kakoee et al , 2014 as well as hardware for monitoring specific modules, such as the router arbiters or datapath components [Seitanidis et al 2014]. A well-established technique to the problem of compromised/corrupted transmission of packets between routers is the use of Error Detecting/Correcting Codes (EDC/ECC).…”

Section: Detection/localizationmentioning

confidence: 99%

“…The BIST process may be executed by the manufacturer prior to shipment, or it may constitute part of system boot-up [Strano et al 2011;Hosseinabady et al 2007]. Runtime BIST is also possible, but system operation is (partially) halted while the module under test is examined [Fick et al 2009b;Kakoee et al 2011a].…”

Section: Introductionmentioning

confidence: 99%

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Chrysanthou

Englezakis

Prodromou

et al. 2016

ACM Trans. Archit. Code Optim.

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Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose NoCAlert, a comprehensive online and real-time fault detection and localization mechanism that demonstrates 0% false negatives within the interconnect for the fault models and stimulus set used in this study. Based on the concept of invariance checking, NoCAlert employs a group of lightweight microchecker modules that collectively implement real-time hardware assertions. The checkers operate concurrently with normal NoC operation, thus eliminating the need for periodic, or triggered-based, self-testing. Based on the pattern/signature of asserted checkers, NoCAlert can pinpoint the location of the fault at various granularity levels. Most important, 97% of the transient and 90% of the permanent faults are detected instantaneously, within a single clock cycle upon fault manifestation. The fault localization accuracy ranges from 90% to 100%, depending on the desired localization granularity. Extensive cycle-accurate simulations in a 64-node CMP and analysis at the RTL netlist-level demonstrate the efficacy of the proposed technique.

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“…Please note that, fault diagnosis is out of scope of this paper. We assume that in the network a hardware [20] [21] or software [22] diagnosis mechanism exists to detect faults. We further assume that the availability of a channel c i,j = (U 0,i , U 0,j ) is signaled by availability signal κ i,j that leads in the reverse direction of the channel, i.e.…”

Section: Recalculation Of Routingmentioning

confidence: 99%

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

Schley

Radetzki

2015

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

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With increasing number of processing elements on a single chip, the size of the Network-on-Chip connecting the processing elements increases accordingly. This leads to new challenges for components such as fault diagnosis and routing because they do not scale with the size of the Network-on-Chip, e.g. regarding the required communication overhead or their implementation costs. A measure to avoid these scaling problems is to organize future Networks-on-Chip hierarchically.This paper presents a fault tolerant routing for Networks-on-Chip organized into hierarchical units where each unit manages its own routing. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16x16 network show a speedup of three for routing reconfiguration compared to state-of-the-art approach. At the same time our approach achieves a memory reduction for routing tables by a factor of seven compared to flat network tables.

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A distributed and topology-agnostic approach for on-line NoC testing

Cited by 51 publications

References 22 publications

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip

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