A disturb-alleviation scheme for 3D flash memory

Chang, Yang-Lang; Chang, Yuan-Hao; Kuo, Tei-Wei; Li, Hsiang-Pang; Li, Yung-Chun

doi:10.1109/iccad.2013.6691152

Cited by 20 publications

(5 citation statements)

References 12 publications

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“…However, although 3D flash memories present a good opportunity to further increase the capacity as well as reduce the bit cost, some research reports from the industries and the academics have pointed out that multiple potential problems impose huge challenges on adopting 3D flash memories in a typical storage system [22], [81], [76]. In particular, big block [76], [22] and program disturbance [22], [81] are two critical issues that should be considered for garbage collection and wear-leveling.…”

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 98%

“…Want et al [81] proposed to eliminate inter-block disturbance by means of creating a physical distance between neighboring logical blocks. On the contrary, Chang et al [22] proposed a new life cycle of physical block to avoid writing pages whose adjacent pages currently contain valid data so as to reduce intra-block disturbance. Even though those works could resolve the disturbance to a certain degree, they might face new challenges on fulfilling the requirement of garbage collection and wear-leveling.…”

Section: B Program Disturbance Problemmentioning

confidence: 98%

“…In particular, big block [76], [22] and program disturbance [22], [81] are two critical issues that should be considered for garbage collection and wear-leveling. In the following sections, we will discuss the impact of these two problems on performing garbage collection or wear-leveling respectively in Section IV-A and Section IV-B.…”

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 99%

“…Thus, the accumulated hot data possibly become sequential data after a period of time since writing back sequential data to flash memories is beneficial to garbage collection and wear-leveling. Besides, the proposed half block management in [22] aims to simulate each half block as a physical block to flash translation layer. Such design is able to postpone the timing of issuing erase operations so as to reduce the average latency in garbage collection or wear-leveling for a full big block.…”

Section: A Big Block Problemmentioning

confidence: 99%

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Garbage collection and wear leveling for flash memory: Past and future

Yang

Chang

Tsao

et al. 2014

2014 International Conference on Smart Computing

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Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in nonvolatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious writeonce property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

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Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 98%

Section: B Program Disturbance Problemmentioning

confidence: 98%

Section: Design Issues In 3d Flash Memory Storagementioning

confidence: 99%

Section: A Big Block Problemmentioning

confidence: 99%

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Garbage collection and wear leveling for flash memory: Past and future

Yang

Chang

Tsao

et al. 2014

2014 International Conference on Smart Computing

Self Cite

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“…Other optimization schemes such as an initial channel precharge phase [357] and selector doping [358] have been also proposed. In analogy with planar devices, suitable management schemes for 3D NAND have been also proposed [359,360]. Similar considerations apply to vertical-gate structures, in which channel arrays are horizontally stacked with vertical WLs [361,362].…”

Section: Disturbsmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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