A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

Abstract

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices

“…Dynamic P&R is a self-repair technique with on-the-fly partial placement and routing (P&R) [9]. Pre-compiled reconfiguration selects a proper configuration from ones that were prepared beforehand and loads it [10]. The attainable reliability and MTTF enhancement and necessary hardware overhead are different among these methods [3].…”

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures

“…Reference [7] proposed a fault recovery technique by selecting a proper configuration from ones prepared beforehand and reloading it. This idea of (e) pre-compiled reconfiguration is implemented as shown in Fig.…”

“…For reconfigurable devices, several methods to replace faulty BEs have been proposed. On FPGA, references [5][6][7] proposed fault tolerance techniques using spare logic blocks. Similar approaches that utilize spares for replacement are investigated for coarse grained reconfigurable devices [8] and homogeneous many-core systems with network-on-chip [9].…”