A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures

Abstract

Field Programmable Gate Array (FPGA) architectures are suitable hardware platforms for systems that need high performance and flexibility, because they support dynamic partial reconfiguration (DPR) to implement adaptive hardware algorithms e.g., for performance or energy efficiency. They are used for example in embedded systems such as UAV, e.g. for video processing. It is a challenge to design Autonomic Managers for such highly dynamic systems, taking into account the combinatorial design space of configurations and criteria and policies to decide on whether to reconfigure, and what next configuration to choose. In this paper, we propose a Domain Specific Language (DSL) called Ctrl-DPR, allowing designers to easily generate Autonomic Managers. They can describe their system and their management strategies, in terms of the entities composing the system : tasks, versions, applications, ressources, policies. The DSL relies on a behavioural modelling of these entities, targeted at the design of autonomic managers to control the reconfigurations in such a way as to enforce given policies and strategies. The models we use involve automata to describe the state space of configurations, and the transitions representing reconfigurations; they also involve discrete control techniques exploiting such models in order to obtain a correct runtime manager. These model-based control techniques are embedded in a compiler, connected to a reactive language and discrete controller synthesis tool, which enables to generate a C implementation of the controller enforcing the management strategies. We apply our DSL for the management of a video application on a UAV.

Autonomic Management of Reconfigurations in DPR FPGA-based Embedded System

“…The Perspectives are in several directions, amongst which we are currently implementing the case study of a video tracking system on a DPR FPGA, for which the bitstream implementations are ongoing. Moreover we are definining a DSL [6] allowing to describe architecture and application and objectives for automatic generation of the automata models and generation of the manager runtime code. We will exploit modularity supported by Heptagon/BZR [5] to control complex DPR FPGA architectures for scalability of design space exploration.…”