A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication

Muzaffar, Shahzad; Elfadel, Ibrahim M.

doi:10.1109/tvlsi.2019.2911393

Cited by 4 publications

(2 citation statements)

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“…This paper is a major expansion of our earlier conference publication [13] with novel and original material added throughout. The expansion takes into account our most recent work on ECS protocols, especially [3], as well as our most recent work on domain-specific hardware design for IoT communication interfaces [14].…”

Section: ) Packet Encryptionmentioning

confidence: 99%

“…It is therefore concluded that the crypto overhead in ECS is essentially driven by the data rate with maximum data rate achieved using a single-clock-cycle crypto implementation. Finally, we would like to point out the secure ECS design alternative based on the domain-specific instruction set architecture, PICIA, proposed in [14]. A crypto ISA extension along with the supporting HSA5/1 crypto block can be added to PICIA that combines both the flexibility of a securely programmable IoT communication interface with the lowpower, high data-rate features of ECS.…”

Section: Secure Ecs Design Alternativesmentioning

confidence: 99%

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Lightweight, Single-Clock-Cycle, Multilayer Cipher for Single-Channel IoT Communication: Design and Implementation

et al. 2021

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The area of lightweight cryptography for constrained nodes has been quite well researched since the advent of RFID tags. However, the important issue of the integrated design of a secure, ultralow power, small-footprint IoT transceiver has not received sufficient attention. The objective of this paper is to present such a transceiver and evaluate its data rate and power in the presence of the cryptographic overhead and compare its security with that of prior lightweight cryptographic algorithms. The proposed secure transceiver design is based on two main novel ingredients. The first is the Edge-Coded Signaling (ECS) protocol -a recently introduced technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. The second ingredient is a novel high-speed symmetric block cipher, HSA5/1, that is based on the well-known A5/1 cipher and that generates a full keystream in one clock cycle. Both ingredients are combined to design a lightweight, high-speed, multilayer cipher with a tunable impact on ECS's power consumption, energy efficiency, and data rate. The multilayer cipher provides additional layers of packet security that make it difficult for an attacker to even receive a legitimate packet, let alone decrypt its data by attacking the HSA5/1 protocol itself. In addition, the multilayer encryption method may be easily configured to modulate the communication security overhead as a function of the number of clock cycles made available to the encryption/decryption stage. The secure ECS transceiver is prototyped and verified on both an embedded and an FPGA platform. It has also been synthesized for an ASIC implementation in 65nm CMOS technology that is shown to preserve the lowpower operation of ECS, consuming only 27µW of power at a clock frequency of 25M Hz while requiring only one clock cycle for executing 148-bit-key encryption/decryption unit.

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Section: ) Packet Encryptionmentioning

confidence: 99%

Section: Secure Ecs Design Alternativesmentioning

confidence: 99%