A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

Lung, Hsiang-Lan; Miller, Christopher P.; Chen, Chia‐Jung; Lewis, S.H.; Morrish, J.; Perri, T.; Jordan, Richard C.; Ho, H. Y.; Chen, Tu-Shun; Chien, Wei-Ming; Drapa, Mark; Maffitt, T.; Heath, J.R.; Nakamura, Yutaka; Okazawa, Junka; Hosokawa, Kohji; BrightSky, M.; Bruce, Robert L.; Cheng, Huai-Yu; Ray, A.; Ho, Yung-Han; Yeh, Chau‐Shioung; Kim, Wanki; Kim, Sang-Bum; Zhu, Yu; Lam, C.

doi:10.1109/imw.2016.7493563

Cited by 9 publications

(7 citation statements)

References 4 publications

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“…where T P CM/ST T −MRAM is the time needed to write that memory. The recovery time calculated with ( 7) is longer than that of the first hybrid architecture, but comparing with that of state-of-the-art SSD it is found that by using fast M-class PCM like [72] or STT-MRAM like [116] such value could be up to ten or twenty times lower. In both cases the power loss reliability will be improved.…”

Section: B the Power Loss Recovery Casementioning

confidence: 93%

“…The most common selectors for PCM are MOSFETs [34], [67], BJTs [68], [69], or diodes [70], [71]. MOSFETs severely limits the integration density due to the high area occupation (i.e., up to 22 F 2 in order to provide a reasonable RESET current) [60], [67], [72]. BJTs are the preferred solution in 1T-1R (i.e., one transistor-one resistor) architectures since they are able to provide acceptable current densities for the RESET operation at an area occupation expense of 5.5-8 F 2 if integrated vertically [68].…”

Section: B Performance and Reliabilitymentioning

confidence: 99%

“…However, figures of merit of this technology are harder to benchmark against a DRAM, but once again are appealing for NOR Flash replacement. In [72], by using a novel multiple individual bank sensing/writing and a memory bank interleave design, it was demonstrated a DDR2 DRAM-like interface PCM. The write and read bandwidth on this chip are equal to 533 MB/s, and the random read latency is 37.5 ns, whereas the write latency is 11.25 ns.…”

Section: B Performance and Reliabilitymentioning

confidence: 99%

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Phase Change and Magnetic Memories for Solid-State Drive Applications

et al. 2017

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The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate nand Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, nand Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability

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Section: B the Power Loss Recovery Casementioning

confidence: 93%

Section: B Performance and Reliabilitymentioning

confidence: 99%

Section: B Performance and Reliabilitymentioning

confidence: 99%

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Phase Change and Magnetic Memories for Solid-State Drive Applications

et al. 2017

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“…However, higher the number of bitline cells, higher is the IR drop. The trade-off point is typically set to 4096 cells in most PCM designs [8,51,66,79]. Similar analysis conducted on Micron's 45nm DRAM design suggests 2 NVM, like DRAM, is organized hierarchically.…”

Section: Introductionmentioning

confidence: 99%

Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories

Song,

Das,

Kandasamy

2020

Preprint

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Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory.We show that our hybrid tiered-memory architecture has a tremendous potential to improve performance and reliability, if exploited by an efficient page management policy at the operating system (OS). Modern OSes are already aware of inter-memory asymmetry. They migrate pages between the two memory types during program execution, starting from an initial allocation of the page to a randomly-selected free physical address in the memory. We extend existing OS awareness in three ways. First, we exploit both inter-and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial

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“…However, PCM has finite write endurance, and its access latency and energy are higher than those of DRAM [29,30,58,60,77,103,107,118]. One key characteristic of PCM is the asymmetry in read and write latencies [77,86,141]. This is because the SET operation (0 → 1 programming) in PCM requires longer latency than the RESET operation (1 → 0 programming).…”

Section: Introductionmentioning

confidence: 99%

Improving Phase Change Memory Performance with Data Content Aware Access

Song,

Das,

Mutlu

et al. 2020

Preprint

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Phase change memory (PCM) is a scalable non-volatile memory technology that has low access latency (like DRAM) and high capacity (like Flash). Writing to PCM incurs significantly higher latency and energy penalties compared to reading its content. A prominent characteristic of PCM's write operation is that its latency and energy are sensitive to the data to be written as well as the content that is overwritten. We observe that overwriting unknown memory content can incur significantly higher latency and energy compared to overwriting known all-zeros or all-ones content. This is because all-zeros or all-ones content is overwritten by programming the PCM cells only in one direction, i.e., using either SET or RESET operations, not both.In this paper, we propose data content aware PCM writes (DATACON), a new mechanism that reduces the latency and energy of PCM writes by redirecting these requests to overwrite memory locations containing all-zeros or all-ones. DATACON operates in three steps. First, it estimates how much a PCM write access would benefit from overwriting known content (e.g., all-zeros, or all-ones) by comprehensively considering the number of set bits in the data to be written, and the energy-latency trade-offs for SET and RESET operations in PCM. Second, it translates the write address to a physical address within memory that contains the best type of content to overwrite, and records this translation in a table for future accesses. We exploit data access locality in workloads to minimize the address translation overhead. Third, it re-initializes unused memory locations with known allzeros or all-ones content in a manner that does not interfere with regular read and write accesses. DATACON overwrites

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A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

Cited by 9 publications

References 4 publications

Phase Change and Magnetic Memories for Solid-State Drive Applications

Phase Change and Magnetic Memories for Solid-State Drive Applications

Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories

Improving Phase Change Memory Performance with Data Content Aware Access

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