A Double Node Upset Tolerant Memory Cell

Abstract

Abstract. As we enter the deep submicron era, the steadily shrinking feature sizes make charge sharing much easier among physically adjacent nodes in integrated circuits, which ultimately results in DNU (Double Nodes Upset). In this paper, we propose a 16-transistor memory cell. Hspice simulation shows this cell maintains its original logic status under SNU (Single Node Upset) and DNU, while DICE (Dual Interlock CEll) and Quatro-10T cell may fail. Besides, the 16T cell reduces the circuit area by 33.33%, compared to the other two DNU tolerant cells, Delta DICE and DONUT.