A DPLL-based per core variable frequency clock generator for an eight-core POWER7&lt;sup&gt;&amp;#x2122;&lt;/sup&gt; microprocessor

Tierno, J.; Rylyakov, Alexander V.; Friedman, Daniel; Chen, Ann; Ciesla, Anthony; Diemoz, Timothy; English, George; Hui, David; Jenkins, K.A.; Muench, Paul; Rao, G. T.; Smith, G.J.; Sperling, Michael; Stawiasz, K.

doi:10.1109/vlsic.2010.5560342

Cited by 23 publications

(13 citation statements)

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“…The corresponding architecture, as shown in Fig.1 clock generator (CG) accordingly in each cycle. Such a CG can for example be realized in form of a tunable ring oscillator with a muxed clock output [9], [10] or via a multi-PLL clocking unit such as the one proposed in [11], which is thus beyond the scope of this paper. We note that the design of an appropriate CG can have a significant influence on the system power consumption, and requires special care.…”

Section: A Instruction Based Clock Adjustmentmentioning

confidence: 99%

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Constantin

Wang

Karakonstantis

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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. (2015). Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. In ProceedingsDesign, Automation and Test in Europe, 2015 (pp. 381-386 Publisher rights © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. General rightsCopyright for the publications made accessible via the Queen's University Belfast Research Portal is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Abstract-Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28 nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

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Section: A Instruction Based Clock Adjustmentmentioning

confidence: 99%

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Constantin

Wang

Karakonstantis

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…Furthermore, the logic synthesis feature of the digital PLL reduces the design time and has better programmability, portability, and testability when the PLL is converted to different CMOS process technologies. As a result, digital PLLs have recently gained broad interest as an alternative to conventional analog charge-pump based PLLs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, the bang-bang digital PLL (BB-DPLL) has been widely researched as an attractive topology for a clock generator for SoC applications owing to its simple implementation and small area [9][10][11][12][13][14][15]. Figure 2 shows a top-level diagram of a conventional BB-DPLL.…”

Section: Introductionmentioning

confidence: 99%

“…In the conventional digital PLL, a sigma-delta modulator, which produces high-speed dithering streams to improve the effective frequency resolution of a digitally controlled oscillator (DCO), is used for the fractional dithering circuit. To suppress spurious tones, digital PLLs adopt the high-order sigma-delta modulator which randomizes dithering streams [2,11,12].…”

Section: Introductionmentioning

confidence: 99%

“…Copyright ⓒ2016 SERSC Among several DCO topologies, a ring-based DCO circuit with a large unit gain is most commonly adopted to achieve a wide frequency-locking range, a small chip area, and a fast lock time for the clock generator [10][11][12][13][14]. However, when the high-order sigma-delta modulator is applied to a ring-based DCO with a large unit gain, its quantization noise becomes the dominant contributor to increase the jitter and PLL phase noise in the high-frequency offset region.…”

Section: Introductionmentioning

confidence: 99%

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Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

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2016

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A 0.012 mm2 and 2.5 mW bang–bang digital PLL using pseudo random number generator

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A DPLL-based per core variable frequency clock generator for an eight-core POWER7<sup>™</sup> microprocessor

Cited by 23 publications

References 3 publications

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

A 0.012 mm2 and 2.5 mW bang–bang digital PLL using pseudo random number generator

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