A Drain Current Model Based on the Temperature Effect of a-Si:H Thin-Film Transistors

Qiang, Lei; Yao, Ruohe

doi:10.1088/0256-307x/29/9/097301

Cited by 5 publications

(2 citation statements)

References 30 publications

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“…In the case of multiple trapping conduction, the drain current obeys the Meyer-Neldel rule. It can be described using the following equation [11,12]:…”

Section: Resultsmentioning

confidence: 99%

Analysis of Carrier Transport Mechanism for p-Type SnO Thin-Film Transistor

Qin

Qiang²

2017

KEM

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Temperature effect on the I-V characteristics of tin monoxide thin film transistors (SnO TFTs) has been analyzed. The result shows that the drain current of the SnO TFT obeys the Meyer-Neldel rule under low temperature, where current conduction is a thermally activated process. The carrier transport would be dominated by multiple trapping conduction, while, percolation conduction mechanism holds as the temperature increase.

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“…In the case of multiple trapping conduction, the drain current obeys the Meyer-Neldel rule. It can be described using the following equation [11,12]:…”

Section: Resultsmentioning

confidence: 99%

Analysis of Carrier Transport Mechanism for p-Type SnO Thin-Film Transistor

Qin

Qiang²

2017

KEM

Self Cite

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“…where 𝑉 FB is the flat band voltage, 𝜇 BAND is the flat band mobility, 𝑉 G is the gate voltage, and 𝛾 is a material-and temperature-dependent parameter. [14] Synchronous dual-gate mode means that the top gate electrode and the bottom gate electrode are connected (i.e., 𝑉 BG = 𝑉 TG = 𝑉 G ).…”

mentioning

confidence: 99%

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

Li¹,

Liao²,

Tian-Bao³

et al. 2018

Chinese Phys. Lett.

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An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) with dual-gate structures is developed. The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges, which are controlled by gate voltage. It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance (𝐶TI/𝐶BI). Incorporating the proposed model with Verilog-A, a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations. Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

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