A DSL customer-premise equipment modem SoC with extended reach/rate for broadband bridging and routing

Abstract

et al. Texas Instruments Bangalore and Texas Instruments, Dallas, TXThis single chip DSL CPE Modem supports multifarious standards like G.dmt.992 Annex A, B, C, G.dmt.bis, and the upcoming ADSL+ and Extended Reach requirements. The full chip consists of a C62x TM based DSL PHY, AFE, Line Driver and Receiver, power management, and broadband controller subsystem for an end-to-end Bridge/Router for residential gateway applications, as shown in Fig. 18.7.1. The chip is implemented in 0.13µm 5M CMOS technology that supports high speed digital operation at 1.5V, analog at 3.3V, and drain extended transistors for 12V line driver functions. DSL PHY subsystem:The DSL PHY consists of AFE and digital signal processing subsystems. The digital signal processing subsystem consists of a 200MHz C62x TM DSP CPU, program/data memories and hardware accelerators. All of the necessary operations such as time domain equaliziation, echo cancellation, FFT/IFFT operations, Trellis, Reed Solomon, decimation, interpolation, and filtering functions required on the transmit and receive paths can be realized using this configuration. The hardware accelerators provide hooks for dynamic adaptive equalization that enable higher data rates. The programmability of modules enables support of multiple modes like G.lite, G.dmt, and ADSL+ over POTS/ISDN lines, and interoperability with the various CO modems. In addition, the subsystem has a multichannel serial interface, a multi-channel DMA engine, and network timing reference (NTR) generator as peripherals. Analog Front End (AFE) Subsystem:The AFE consists of transmit and receive channels in addition to the timing recovery blocks. The transmit channel consists of programmable digital interpolation filters, a 4.4MS/s, 14b current steering DAC with 70dB multi-tone power ratio (MTPR), an I-V converter, an analog reconstruction filter, and a 12V line driver. The combination of digital filters and the analog LPF with in-band cutoff frequencies, coupled with integration of the line driver in the last filter stage, enables a -140dBm/Hz out-of-band noise performance for the transmit channel (Fig 18.7.2). The receive channel is comprised of a third order HPF to attenuate the transmit echo, an analog equalizer, an anti-aliasing LPF, and a 35.328MSPS Σ∆ A/D converter. The low noise receiver integrated with the HPF also provides programmable gain with less than 2nV/rtHz input referred noise. The ADC uses a 5-level quantizer in the first stage, 3-levels in the 2nd stage, and has an MTPR of 65dB, as shown in Fig. 18.7.3. Programmability for all analog and digital filters to suit 138kHz and 276kHz corner frequencies enables the support of both ISDN and POTS standards. An integrated digitally controlled crystal oscillator with +/-150ppm range helps in eliminating the external micro-clock voltage controlled crystal.Networking subsystem: The networking subsystem consists of MIPS32 TM 4KEc TM core, 4-way Set Associative I/D Cache operating at 160 MHz, and networking peripherals such as a USB controller, a 10/100 Ethern...

An ADSL2 and VDSL2 CPE System-on-Chip with Integrated Voice over IP Capabilities for Residential Gateway Applications

“…Also, the presence of large switching blocks and high speed IO posed challenge to the performance of the Data Converters. Low noise techniques [1] were used to ensure that such coupling is minimized.…”