2017
DOI: 10.1109/jssc.2017.2718665
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A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

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Cited by 16 publications
(5 citation statements)
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“…In order to reduce the FPN of the prototype APD, the off-chip digital offset adjustment was performed as in Refs. [20,21] so that the variation of APD can be reduced from 3.9 % to less than 0.1 % as shown in Figure 16. However, as the InGaAs APD was implemented as 16 partitioned cells in the prototype chip, the variation of APD is larger than the conventional one inducing the fixed pattern noise (FPN) [19], as shown in Figure 15a,b).…”
Section: Measurement Resultsmentioning
confidence: 98%
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“…In order to reduce the FPN of the prototype APD, the off-chip digital offset adjustment was performed as in Refs. [20,21] so that the variation of APD can be reduced from 3.9 % to less than 0.1 % as shown in Figure 16. However, as the InGaAs APD was implemented as 16 partitioned cells in the prototype chip, the variation of APD is larger than the conventional one inducing the fixed pattern noise (FPN) [19], as shown in Figure 15a,b).…”
Section: Measurement Resultsmentioning
confidence: 98%
“…In order to reduce the FPN of the prototype APD, the off-chip digital offset adjustment was performed as in Refs. [20,21] so that the variation of APD can be reduced from 3.9 % to less than 0.1 % as shown in Figure 16.…”
Section: Measurement Resultsmentioning
confidence: 98%
“…This made it difficult to clarify the distinct range information. In order to reduce the pixel FPN of the prototype APD, off-chip digital offset adjustment was performed as off-chip calibration as in [17,23], so that the offset difference between neighboring pixels could be reduced to under 1 LSB. After offset adjustment, the pixel FPN was reduced to less than 0.1%.…”
Section: Measurement Results and Discussionmentioning
confidence: 99%
“…Various studies have been reported on low-power circuit design [5]- [7] in literature for specific operating conditions. In addition, low-power readout techniques that are optimized for the characteristics of input signals [8]- [10] and specific operations related to applications [11]- [14] have been reported. For example, Park et al [7] achieved low power consumption by adopting a fully dynamic CIS structure; however, this structure is not suitable for high-speed operation because it suffers from high readout noise due to increased global supply signal and power-line fluctuations.…”
Section: Introductionmentioning
confidence: 99%