A dual-mode weight storage analog neural network platform for on-chip applications

Abstract

On-chip trainable neural networks show great promise in enabling various desired features of modern integrated circuits (IC), such as Built-In Self-Test (BIST), security and trust monitoring, self-healing, etc. Cost-efficient implementation of these features imposes strict area and power constraints on the circuits dedicated to neural networks, which, however, should not compromise their ability to learn fast and retain functionality throughout their lifecycle. To this end, we have designed and fabricated a reconfigurable analog neural network (ANN) chip which serves as an expertise acquisition platform for various applications requiring on-chip ANN integration. With this platform, we intend to address the key cost-efficiency issues: a fully analog implementation with strict area and power budgets, a learning ability of the proposed architecture, fast dynamic programming of the weight memory during training, and high precision non-volatile storage of weight coefficients during operation or standby. We explore two learning structures: a multilayer perceptron (MLP) and an ontogenic neural network with their corresponding training algorithms. The core circuits are biased in weak inversion and make use of the translinear principle for multiplication and non-linear conversion operations. The chip is mounted on a custom PCB and connected to a computer for chip-in-the-loop training. We present measured results of the core circuits and the dual-mode weight memory. The learning ability is evaluated on a 3-input XOR classification task.

A Survey of Neuromorphic Computing and Neural Networks in Hardware

“…Other gradient descent-based optimization methods have also been implemented on neuromorphic systems for training, and they tend to be variations of back-propagation that have been adapted or simplified in some way [639], [645], [709], [716], [718], [719], [723], [792], [812], [844], [1030], [1122], [1300]- [1303]. Back-propagation methods have also been developed in chip-in-the-loop training methods [686], [702], [732], [815], [859]; in this case, most of the learning takes place on a host machine or off-chip, but the evaluation of the solution network is done on the chip. These methods can help to take into account some of the device's characteristics, such as component variation.…”

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

“…Artificial neural network (ANN)-based machine learning, known as a promising technology, has been researched widely to enable electronic devices more intelligent and efficient [ 1 , 2 , 3 , 4 ]. ANN is inspired by the brain of living creatures, which contains components such as neurons, connections, weights, and a propagation function.…”

An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs

“…The key contribution of this paper is the development of a custom neural platform targeting the specific design requirements outlined above. The design represents a major revision of an earlier version [9] with improved circuit-and systemlevel characteristics. The architecture supports two popular learning models, namely the multilayer perceptron (MLP) and the ontogenic neural network (ONN).…”