A durable and energy efficient main memory using phase change memory technology

Abstract

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories -- the Phase Change Memory (PCM) as the main memory for a 3D stacked chip. The main challenges we face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology. We propose techniques to extend the endurance of the PCM to an average of 13 (for MLC PCM cell) to 22 (for SLC PCM) years. We also study the design choices of implementing PCM to achieve the best tradeoff between energy and performance. Our design reduced the total energy of an already low-power DRAM main memory of the same capacity by 65%, and energy-delay 2 product by 60%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

Fast Persistent Heap Based on Non-Volatile Memory

“…PCM also has some drawbacks such as low write speed and poor endurance. There are many studies at architectural level to address these problems [11]- [14]. In this paper we assume the wear-leveling is done in the memory controller.…”

Increasing PCM main memory lifetime

“…SS is done by swapping two segments: the one currently being written and the one that is least-frequently-written (LFW). However, the large segment size (1MByte) used in SS [5] degrades lifetime compared to a small segment size because the distribution of writes to a large segment can be skewed. Nevertheless, large segments are used in [5] to reduce the costs associated with searching for the LFW segment during a swap.…”

“…As main memory has become a primary energy consumer [1], many lowpower memory systems have been proposed that use new technologies as replacements for DRAM [2], [3], [4]. One technology that has potential is Phase-Change Memory (PCM) due to its low energy, good read performance, nonvolatility and bit addressability [5], [4], [3], [2], [6]. However, PCM poses challenges that have to be addressed for it to be used as a main memory replacement.…”

“…However, the large segment size (1MByte) used in SS [5] degrades lifetime compared to a small segment size because the distribution of writes to a large segment can be skewed. Nevertheless, large segments are used in [5] to reduce the costs associated with searching for the LFW segment during a swap.A system level approach is used in [3] to incorporate PCM in the memory hierarchy. This work proposes a hybrid memory, where a large PCM memory is augmented with a small DRAM that acts as a "page cache" for the PCM memory.…”

“…Second, read-Write-Read (RWR) and page partitioning techniques are used to remove unnecessary writes and act as a failure detection mechanism. This technique is similar to device-level write differencing [10], [5]; however, our …”