A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System

Lee, Yu-Huei; Yang, Yao-Yi; Chen, Ke-Horng; Lin, Ying-Hsi; Wang, Shih Jung; Zheng, Kuo-Lin; Chen, Po-Fung; Hsieh, Chun-Yu; Ke, Yu-Zhou; Chen, Yi-Kuang; Huang, Chien‐Lin

doi:10.1109/jssc.2010.2063610

Cited by 42 publications

(7 citation statements)

References 23 publications

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“…Thus, the currents I 1 and I 2 can be derived as (2). When the inductor current is affected by a small duty perturbation, d 1 (t), the inductor current variation can be calculated as (3). If the HSNR comparator deliver same power to negative voltage, the relationship between d 1 (t) and d 2 (t) would be derived by (2) and (3).…”

Section: Control Loop Analysis For the Positive Output Voltagementioning

confidence: 99%

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A single-inductor bipolar-output converter with 5 mV positive voltage ripple for active matrix OLED

Chen

Chiu

Hsieh

et al. 2011

2011 IEEE Energy Conversion Congress and Exposition

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This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30mΩ, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA

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Section: Control Loop Analysis For the Positive Output Voltagementioning

confidence: 99%

“…In general, the bipolar outputs are obtained by integrating two independently controlled converters in a single chip [1][2][3][4][5][6][7][8]. The boost converter is utilized for positive output voltage, and the negative output voltage is generated by inverting buck-boost converter.…”

Section: Introductionmentioning

confidence: 99%

A single-inductor bipolar-output converter with 5 mV positive voltage ripple for active matrix OLED

Chen

Chiu

Hsieh

et al. 2011

2011 IEEE Energy Conversion Congress and Exposition

Self Cite

View full text Add to dashboard Cite

show abstract

“…In recent years, a rapid growth of portable devices, such as smartphones, tablets, laptops and digital cameras is resulted from the development of system-on-chip (SoC) [1]- [8] which have different energy requirements [6]- [9]. Concurrently, low power consumption is one of the primary design agenda for the battery-powered SoC [10]. Switching converters are widely used due to its high power-conversion efficiency [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

A 40nm CMOS Hysteretic Buck DC-DC Converter With Digital-Controlled Power-Driving-Tracked-Duration Current Pump

2020

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“…Recently, DVS is utilised for not only digital systems such as memory [1,2] and digital signal processor [3][4][5] but also analogue systems or mixed-mode systems including analogue building blocks. For example, a digital-to-analogue converter (DAC) [6] and an ultra-wideband (UWB) system-on-a-chip (SoC) [7] could save much power by using DVS.…”

Section: Introductionmentioning

confidence: 99%

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

Byun

2016

IET Circuits, Devices & Systems

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This paper presents a low-power complementary metal-oxide-semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 2 31 −1 pseudorandom binary sequence is used, the measured bit error rate is better than 10 −12 , the measured JTOL is 0.3 UI pp and the measured jitter of the recovered clock is 6.1 ps rms .

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A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System

Cited by 42 publications

References 23 publications

A single-inductor bipolar-output converter with 5 mV positive voltage ripple for active matrix OLED

A single-inductor bipolar-output converter with 5 mV positive voltage ripple for active matrix OLED

A 40nm CMOS Hysteretic Buck DC-DC Converter With Digital-Controlled Power-Driving-Tracked-Duration Current Pump

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

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