A dynamic CDMA network for multicore systems

Mostafaei

et al. 2021

JTS

CDMA is an important and basic part of today's communications technologies. This technology can be analyzed efficiently by reducing the time, computation burden, and cost by characterizing the physical layer with a Markov Model. Waveform level simulation is generally used for simulating different parts of a digital communication system. In this paper, we introduce two different mathematical methods to model digital communication channels. Hidden Markov and Semi Hidden Markov models' applications have been investigated for evaluating the DS-CDMA link performance with different parameters. Hidden Markov Models have been a powerful mathematical tool that can be applied as models of discrete-time series in many fields successfully. A semi-hidden Markov model as a stochastic process is a modification of hidden Markov models with states that are no longer unobservable and less hidden. A principal characteristic of this mathematical model is statistical inertia, which admits the generation, and analysis of observation symbol contains frequent runs.

Section: Figurementioning

confidence: 99%

Evaluating the CDMA System Using Hidden Markov and Semi Hidden Markov Models

Mostafaei

et al. 2021

JTS

“…Halak et al [11] initiated dynamic assignment of spreading codes for CDMA users and developed a novel CDMA protocol (D protocol) for dynamic assignment. Two different architectures were proposed for CDMA i.e.…”

Section: Related Workmentioning

confidence: 99%

“…Two different types of overloaded CDMA interconnect (OCI) have been suggested i.e. TDMA-Overloaded CDMA Interconnect (T-OCI) and Parallel-Overloaded CDMA Interconnect (P-OCI) is compared with bus wrappers [10] and parallel implementation CDMA [11]. By combining P-OCI and T-OCI, the speed of CDMA crossbar is improved whereas the overall system gets complicated in terms of area utilization.…”

Section: Related Workmentioning

confidence: 99%

“…The operation of encoding process is same as conventional CDMA but the data is encoded bit wise in parallel manner. The multi-bit sum of data is transferred to the decoder module parallelly [11] therefore one clock cycle is sufficient for the completion of the process of encoding one bit of nodes. The data chips are XORed and added simultaneously from the ports hence the proposed encoder reduces the clock cycles for completion of the encoding process than the standard CDMA.…”

Section: ) Encoder Modulementioning

confidence: 99%

See 1 more Smart Citation

Parallel overloaded CDMA crossbar for network on chip

Dananjayan

2019

FACTA U EE

For high performance of Network on Chip (NoC), Code Division Multiple Access (CDMA) technique is used recently due to its fixed communication delay, reduced area utilisation and low power consumption. The CDMA system uses Walsh based spreading code which improves the bandwidth efficiency. On the contrary, it is not effective when the number of nodes present in the system increases. Overloaded CDMA (OCDMA) is presented for such large network systems. In this paper, OCDMA crossbar is modified and advanced with parallel encoding and decoding operation using orthogonal gold codes for improving the speed of crossbar thereby obtaining high performance in NoC switch. A modified crossbar consisting of extra processing elements is used to enhance the performance of NoC based System on Chip (SoC) system. This work is simulated on Xilinx tool and implemented in Vertex-6 (XC6VLX760) Field Programmable Gate Array (FPGA) device. The proposed work is implemented for four ports, eight ports and sixteen ports with deterministic X-Y routing algorithm in 3 3 NoC design with mesh topology. This NoC switch shows 9.79% improvement in delay and shows 20.76% improvement in power consumption when compared to the existing CDMA NoCs for 8 bit data packet.switch has five input port, five output port (four directional and one local) and crossbar with control module (arbiter). The four bi-directional ports are connected with neighboring switches for transfer of data between the source and destination [4]. The local port is used as a processing element (PE) and is responsible for communication between the port and crossbar.This paper proposes a new method for NoC with fixed latency, reduced system cost and power consumption. Recently, CDMA is used to transfer data between the input and output in NoC switch [5]. Fig.1 depicts the structure of CDMA NoC switch. NoC switch has neither solid design nor standard protocol and hence can be designed flexibly to meet the user requirements. The proposed method is implemented for NoC switch using a CDMA crossbar with 2-D mesh topology and 3 3 NoC designed with deterministic X-Y routing algorithm. The routing of data initially searches along the X-direction of destination router and proceeds to the Y-direction. Depending on the destination availability, the distance between the source and destination switch is calculated and transferred to the neighboring switches. Since each port has FIFO buffer, store and forward packet switching [6] is used for the proposed work. The crossbar is the key module for NoC switch as it affects the switch performance and provides multiple access for the data packets. The primary multiple access technique, Time Division Multiple Access (TDMA) is simple but not efficient for CMP. In TDMA only one port sends the data packet simultaneously leaving the other ports to wait until it releases the physical link, thereby increasing the packet latency. Space Division Multiple Access (SDMA) a dedicated path is created between the ports. CDMA is another traditional multiple access techniq...

“…The evaluation results demonstrate the superiority of the OCI-based NoCs in terms of area and throughput. A CDMA protocol for the dynamic assignment of spreading codewords was presented in [15]. It is demonstrated that the parallel CDMA network has a higher throughput and lower latency than the mesh-based NoC and the TDM bus due to the simultaneous medium access nature of CDMA.…”

mentioning

confidence: 99%

Distributed arbitration scheme for on‐chip CDMA bus with dynamic codeword assignment

2020

Computation and communication are the two most critical aspects affecting the overall system performance of complex integrated circuits. Technology scaling has enabled the integration of a large number of processing elements (PEs), in the form of intellectual property cores, within complex systems-on-chip (SoCs), thus increasing the computation performance of integrated circuits considerably. However, dealing with data communication among the ever-increasing number of PEs in an SoC environment requires faster and more efficient on-chip interconnection architectures [1][2][3][4]. Most interconnect networks in embedded SoCs rely on a traditional shared bus employing time-division multiplexing (TDM) communication protocols to reuse expensive on-chip interconnect resources. A TDM bus is usually accompanied by scheduling and arbitration overheads, which increases the transmission latency [5]. Furthermore, the lack of parallel transmissions makes the scaling of a TDM-bus-based onchip interconnect difficult, because each added PE decreases the bandwidth available to the other PEs. Network-on-chip (NoC) has been proposed to address the scalability, latency, throughput, and reliability issues of TDM on-chip communication [6]. The PEs in an NoC system communicate data packets through routers and communication links arranged in a specific network topology. The locality of interconnections provides a high level of parallelism, because all the links and routers in the NoC can operate simultaneously on different