A dynamic voltage scaled microprocessor system

Burd, Tom; Pering, Trevor; Stratakos, A.; Brodersen, R.W.

doi:10.1109/4.881202

Cited by 728 publications

(356 citation statements)

References 9 publications

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“…Total power consumption was calculated as sum total of leakage and active power for execution of application code, plus mode switch instructions, and their corresponding power penalty. For each operating mode, the power consumption and clock frequency of the processor were determined using the models and parameters adopted from [13,11,2,5,6]. The energy and delay penalty incurred by mode switching were also taken into account.…”

Section: Resultsmentioning

confidence: 99%

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Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Huang

Ghiasi

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature sizes continue to shrink, traditioinal power optimization techniques often neglect its contribution to total system power. In this paper, we present a power-aware compilation methodology that targets an embedded processor with both dynamic voltage scaling (DVS) and adaptive body biasing (ABB) capabilities. Our technique has the unique advantage of optimizing design power by jointly optimizing dynamic and leakage power dissipation. Considering the delay and energy penalty of swithching between processor modes, our compiler generates code with minimum power consumption under deadline constraints. Compared to not performing any optimization, or using DVS alone, our technique improves the power consumption of a number of embedded application kernels by 26%, and 14%, respectively.

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Section: Resultsmentioning

confidence: 99%

“…These two techniques have been tried out on several designs, and significant power improvements have been reported [10,13,11]. However, the potentials of such architectural enhancements would not be fully exploited without an effective mode-switching strategy.…”

Section: Introductionmentioning

confidence: 99%

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Huang

Ghiasi

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…Often the rate of the incoming workload is evaluated by the occupancy of an input buffer. The energy efficiency of DVS architectures is 1 Work performed while author was at the University of Virginia.…”

mentioning

confidence: 99%

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design

Putic

Liang

Calhoun

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to provide long battery lifetimes while maintaining required application performance. Existing scalable architecture design approaches are often limited in scope, focusing either only on circuit-level optimizations or architectural adaptations individually. In this paper, we propose a circuit/architecture codesign methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control. PDVS expands upon prior work by using multiple component-level PMOS header switches to enable fine-grained rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS is able to achieve a wide variety of processing rates to match incoming workload as closely as possible, while each iteration takes less energy to process than on architectures with coarser levels of rate control. Measurements taken from a fabricated 90nm test chip characterize both savings and overheads and are used to inform PDVS synthesis decisions. Results show that PDVS consumes up to 34% and 44% less energy than Multi-VDD and Single-VDD systems, respectively.

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“…Figure 3 and plot transient temperature curves with thermal runaway. 3 It clearly shows that as long as the transient temperature reach the runaway temperature, thermal runaway occurs. Note two starting temperatures, 35 o C and 55 o C, are chosen in Figure 3.…”

Section: Where T Is Temperature and T Is Timementioning

confidence: 99%

“…Voltage scaling [3] is widely applied to reduce system energy consumption. Because both dynamic and leakage energy exhibit strong dependence on supply voltage, quadratic and exponential dependence, respectively [1], any study focused on power and energy must consider voltage scaling for accuracy.…”

Section: Introductionmentioning

confidence: 99%

Modeling of coplanar waveguide for buffered clock tree

Chen¹,

He²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Power is rapidly becoming the primary design constrain for systems ranging from server computers to handhelds. In this paper we study microarchitecture-level power modeling and management with temperature and voltage scaling. We develop an accurate temperature-dependent leakage power model and efficient temperature calculation, and show that leakage energy and total energy can be different by up to 10X and 30% for temperatures between 35 o C and 110 o C, respectively. Given the growing significance of leakage power and its sensitive dependence on temperature, no power modeling at microarchitecture is accurate without considering dynamic temperature calculation. Furthermore, we discuss a new thermal runaway phenomenon induced by the temperature dependent leakage power and show that in the near future thermal runaway could be a severe problem. We also study the microarchitecture level coupled power and thermal management by clock gating and novel active cooling techniques. We show that with thermal constraints, clock gating can increase maximum system clock by up to 1.5X and reduce leakage energy by up to 68.5% compared to the cases without clock gating, and active cooling techniques providing smaller thermal resistance can further increase the maximum clock by a factor of 2.44X.

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A dynamic voltage scaled microprocessor system

Cited by 728 publications

References 9 publications

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design

Modeling of coplanar waveguide for buffered clock tree

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