A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

Fujioka, Yoshichika; Kameyama, Michitaka; Lukáč, Martin

doi:10.1109/dt.2017.8024284

Cited by 4 publications

(7 citation statements)

References 3 publications

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“…The sub-block is formed by multiplying and summing nodes. The technical implementation of these nodes as gates has similar parameters in comparison with the gates of operations of minimal, maximum and literal according to a theoretical evaluation in [51][52][53]. The advantages of GRME based PLA in comparison with Post algebra-based PLA is the best testability.…”

Section: Discussionmentioning

confidence: 99%

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

et al. 2019

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Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed-Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression's construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.Electronics 2020, 9, 12 2 of 14 is required. This is caused by the limitation of the binary data amount that can be transferred. Based on these problems, there are tendencies to consider other approaches that do not focus only on binary data. One such approach is known as multiple-valued logic (MVL), which works with more than two values and thus allows encoding more information in "multi-valued bit" than in case of binary-valued bit in two-valued logic [1,5].In the development of the new innovative approach in computer design, the two main pieces of research should be considered. First of them is technological aiming at the development of new multi-valued logic gates. Another one is mathematical, which deals with the development of new methods based on MVL in logic design. The acceptance and usage of semiconductor technology in computer design was due to the help of the appropriate mathematical tools that were introduced in binary logic, which started with the early work of G. Boole [6] and C.E. Shannon [7]. Its results have been used for the development of methods of logic synthesis in nanotechnology [8,9]. In the case of MVL design, the main priority has been devoted to elaborate logic gates based on 3-valued logic because logic with this radix, i.e., with radix 3, results in almost minimal complexity of multi-valued based hardware [1]. Because of that, this type of logic is also considered in this paper.There were two first independent investigations in multiple-valued logic about 1920 conducted by E. Post [10] and J. Lukasiewicz [11]. However, the fist algebra that was functionally complete for any radix was the Post's algebra. This algebra is based on a totally ordered set M of elements 0 < 1 < . . . < m − 1 and it has defined operations maximum (MAX) that is OR in binary algebra, minimum (...

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Section: Discussionmentioning

confidence: 99%

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

et al. 2019

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“…When the XOFF command is received, the data source completely stops sending packets and resumes it, either after some time specified in the data exchange protocol [5], or after receiving the renewal of transmission from the XON command receiver. The proposed solution (Figure 2) largely eliminates these shortcomings due to a smooth and "advanced event" adjustment of the data transmission rate by the source.…”

Section: Methods 1: Control the Flow Of Data Adjusting The Length Of Pauses Between Packetsmentioning

confidence: 99%

“…There are several levels of management. Inter-node management is associated with the allocation of buffer memory at intermediate nodes (allocation to each direction of a certain number of buffers), which reduces to the restriction of the channel queues lengths [5]. Control "input-output" is aimed at preventing locks.…”

Section: Introductionmentioning

confidence: 99%

Data Flows Management and Control in Computer Networks

AlRababah¹

2018

ijacsa

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In computer networks, loss of data packets is inevitable, because of the buffer memory overflow of at least one of the nodes located on the path from the source to the receiver, including the latter. Such losses associated with overflows are hereinafter referred to as congestion of network nodes. There are many ways to prevent and eliminate overloads; these methods, in the majority, are based on the management of data flows. A special place is taken by the maintenance of packages, taking into account their priorities. The ideas of these solutions are quite simple for their implementation in the development of appropriate software and hardware for telecommunication devices. The article considers a number of original solutions to these problems at a level sufficient for the development of new generations of telecommunication devices and systems such as allowing interrupting transmission of the low-priority packet practically at any stage, then to transmit a high-priority packet and only then resume the interrupted transfer, moreover warning in time the data source about the threat of overloading one or several nodes along the route in the propagation of data packets.

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“…When the XOFF command is received, the data source completely stops sending packets and resumes it, either after some time specified in the data exchange protocol, or after receiving the renewal of transmission from the XON command receiver [1].…”

Section: Prototype Modementioning

confidence: 99%

“…One of the known ways to control the flow of data is explained in Fig. 1, on which a fragment of the computer network is shown and the trace of the data stream transmitted through it is indicated [1].…”

Section: Introductionmentioning

confidence: 99%

Controlling Data Flows in Computer Networks

Aa¹

2018

Preprint

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In computer networks, loss of data packets is inevitable, in particular, because of the buffer memory overflow of at least one of the nodes located on the path from the source to the receiver, including the latter. Such losses associated with overflows are hereinafter referred to as congestion of network nodes. There are many ways to prevent and eliminate overloads; these methods, in the majority, are based on the management of data flows. A special place is taken by the maintenance of packages, taking into account their priorities. The article considers a number of original technical solutions to improve the quality of control and reduce the required amount of buffer memory of network nodes. The ideas of these solutions are quite simple for their implementation in the development of appropriate software and hardware for telecommunication devices.

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A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

Cited by 4 publications

References 3 publications

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Data Flows Management and Control in Computer Networks

Controlling Data Flows in Computer Networks

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