A failure analysis framework of ReRAM In-Memory Logic operations

Brackmann, L.; Jafari, Atousa; Bengel, Christopher; Mayahinia, Mahta; Waser, Rainer; Wouters, Dirk J.; Menzel, Stephan; Tahoori, Mehdi B.

doi:10.1109/itcasia55616.2022.00022

Cited by 1 publication

(2 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, as shown in ref. [48], the failure rate asymmetry for different input combinations cannot be avoided in the MAGIC operation. The origin of this input asymmetry lies in the exploited conditional switching.…”

Section: Simulation Study Of Failure Probability Dependenciesmentioning

confidence: 99%

“…In the following, we study the failure probabilities of all proposed individual CIM logic gates with variability‐aware circuit simulations based on a modified version of a previously published failure investigation framework for stateful and non‐stateful CIM. [ 48,49 ] The simulation allows to investigate more complex operations which offers beneficial insights that are not accessible in the used measurements setup. To achieve this, we use the variability‐aware Juelich‐Aachen resistive switching tools (JART)–VCM–v1b [ 50 ] compact model for simulating VCM‐type ReRAM (based on experimental

\left(\text{HfO}\right)_{2} \left(\text{/TiO}\right)_{2}

from FZ Juelich [ 51 ] ) devices, while for the transistors the 22 nm GlobalFoundries (GF) process design kit (PDK) was used.…”

Section: T–1r Single Logic Gate Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Brackmann,

Ziegler,

Jafari

et al. 2023

Advanced Intelligent Systems

View full text Add to dashboard Cite

Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

show abstract

Section: Simulation Study Of Failure Probability Dependenciesmentioning

confidence: 99%