A failure analysis methodology for revealing esd damage to integrated circuits

Abstract

A range of chemical and physical techniques is required in order to identify the failure sites and failure mchanisms of ICs subjected to ESD transients. The damage features of ESD failures from the field are shown to be similar to those produced by simulated human-body-model testing. A curve tracer technique can be used to predict the location of an ESD failure site in the input or output circuit of an IC. Junction shorts induced by ESD transients form as a result of a combination of heating at the site of second breakdown, together with the heat generated by the discharge current in the discharge path. The ESD sensitivity of a given input or output circuit is dependent on the spacing between the input contact window. and the contact window of the nearest diffusion-to-Vss metallization. KEY WORDS Electrostatic damage Integrated circuit failure analysis * Presented at the 6th annual International EOSIESD Symposium, 1984. Reproduced with the permission of the EOS/ESD Association, P 0 Box 298, Westmoreland, NY 13490, U.S.A.