A family of cells to reduce the soft-error-rate in ternary-CAM

Abstract

Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a ternary content-addressable memory (CAM) design with high immunity to SEU. Conventionally, errorcorrecting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. We propose a family of TCAM cells that reduce the SER at the cost of some area increase. An SER reduction of up to 40% can be obtained with a 18% increase of area; another design reduces the SER by 16% with only a 5% increase in area.

Soft‐error protection of TCAMs based on ECCs and asymmetric SRAM cells

“…A simplified example of an ML in an NOR‐type TCAM is illustrated in Fig. 2 [6, 11]. A possible encoding of the values stored in a TCAM cell is also presented.…”

“…A different option is to follow the methodology proposed in [6] which is based on a specific inter‐coupling between the SRAM cells used to encode a value in a TCAM such that some state combinations become more robust to soft‐errors. The solutions described in [6] cannot be directly applied here since only 0 and 1 values are better protected against soft‐errors while don't care values remain relatively unprotected.…”

“…Several schemes have been proposed to offer protection against soft‐errors in SRAM‐based TCAMs. Circuit‐level solutions presented in [6] are able to reinforce 1 and 0 values stored in the TCAM cells but don't care values are left unprotected. At architectural level, false‐misses can be detected with the help of special redundant structures called Bloom filters [7].…”

Evaluation Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory

“…Work continues on the joint use of correcting codes and the mutual topological arrangement of cells on the chip itself [4] in order to reduce the probability of multi-ple upsets. There are examples of the development of ternary-cells with increased failure resistance [5], [6], which did not become successful, because they were based on the modification of the traditional 6T memory cells by the introduction of additional elements and connections. The reliability of 6-transistor memory cells under exposure to single nuclear particles has significantly deteriorated with the design rules reduced to 65-28 nm for the bulk CMOS technology.…”

Τεχνικές Αντιμετώπισης Μεταβατικών Και Μόνιμων Σφαλμάτων Σε Στοιχεία Μνήμης Στις Σύγχρονες Νανομετρικές Τεχνολογίες

“…Εκτός των μεγάλων επιβαρύνσεων και της αυξημένης πολυπλοκότητας που εισάγει η χρήση μιας μνήμης DRAM, η παραπάνω λύση έχει το πρόβλημα ότι μεταξύ δύο ανανεώσεων της μνήμης, μπορεί να έχει γίνει μια πρόσβαση σε κάποια πληροφορία που έχει αλλοιωθεί από μεταβατικό σφάλμα, οδηγώντας έτσι σε λανθασμένο miss ή match. Μία άλλη λύση [131] χρησιμοποιεί το γεγονός ότι στις μνήμες TCAM υπάρχει μια κατάσταση που είναι άκυρη (invalid), κάνοντας την ασταθή προς όφελος των έγκυρων καταστάσεων με χρήση πυλών περάσματος (pass gates) που σταματούν τη διάδοση των διαταραχών με σημαντικό κόστος στην επιφάνεια. Στο [132] προτείνεται ένα σχήμα κωδικοποίησης το οποίο μπορεί να ανιχνεύσει μόνο λανθασμένα match.…”