A family of Full-Bridge Single-Stage PFCs topologies: Identification of technical problems

Ribeiro, Hugo; Borges, Beatriz; Ferreira, Carlos

doi:10.1109/ecce.2012.6342695

Cited by 3 publications

(1 citation statement)

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“…This fact is due in part to the manufactures inertia in changing their matured solutions and also to the single stage topologies operating limits and complex control issues like the regulation of the DC bus voltage with light load that is one of the most problematic concerns. Referring the FBSS topologies, some of these operating and control restrictions have been identified and solved very recently [36][37], however, some improvements are still needed. One of the most important is the downsizing and the cost reduction associated to the DC bus capacitor.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Voltage-Fed AC–DC Full-Bridge Single-Stage Power Factor Correctors with a Reduced DC Bus Capacitor

Ribeiro

Borges

2014

IEEE Trans. Power Electron.

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Full-Bridge Single-Stage, FBSS, AC-DC converters allow to regulate both the output voltage and the input current that achieves a near sinusoidal waveform using only the four bridge transistors. Independently of this feature, these converters still need to be optimized in order to become an interesting and attractive solution for modern Switch Mode Power Supplies with PFC function. One of the most important improvements needed is the downsizing of the DC bus capacitor, C b , with the inherent cost reduction. However, this action introduces complex issues in the regulation of the input current and it is also responsible for the generation of high output voltage ripple. The new contribution of this paper consists in the introduction of a set of power circuit optimizations and control techniques in a Full Bridge Single-Stage PFC converter that solves the referred issues in order to enable the reduction of the DC bus capacitor's size and cost. These procedures are based in the use of a Free Wheeling Circuit that improves the light load operation and in the application of One Shot non linear modulator, in order reduce the output voltage ripple even when the DC bus ripple is high. The possibility of using, in the proposed topology, a reduced ratio capacitance/watt lower than the typical values used in commercial applications (0.7F/W to 0.5F/W for 385V to 450V respectively), while maintaining the accurate input current regulation, is also theoretically proved. The developed concepts, solutions and design criteria are detailed described in the paper. The correspondent theoretical study is verified trough experimental results token in an optimized FBSS topology prototype.This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. IEEE TRANSACTIONS ON POWER ELECTRONICS 2regulation of the input current, the output voltage and the average DC bus voltage.Considering the above aspects, the proposed paper introduces an additional contribution to the existing similar solutions, presenting new design criteria to reduce the DC bus capacitor size, which result from an exhaustive analysis of the DC bus voltage ripple impact in the input current regulation. The study concludes that the DC bus voltage ripple increase improves the regulation of the input current and that is possible to achieve reduced output voltage ripple, <0.2% of V O , (even with high voltage ripple in C b ) using a modified One Cycle Controller, OCC, with one shot circuit.

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Section: Introductionmentioning

confidence: 99%