A family of variable-precision interval arithmetic processors

Schulte, Michael; Swartzlander, Earl E.

doi:10.1109/12.859535

Cited by 58 publications

(26 citation statements)

References 28 publications

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“…While hardware implementations for general purpose interval arithmetic processors have previously been created [2,3], we have created a customisable library of operators, notably in terms of rounding mode, exponent and mantissa size, so as to exploit the full freedom offered by FPGAs in creating a fully-custom datapath.…”

Section: Introductionmentioning

confidence: 99%

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA

Lann

Boland

Constantinides

2011

Lecture Notes in Computer Science

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Abstract. In the majority of scientific computing applications, values are represented using a floating point number system. However, this number system only considers an approximate value without any indication of the approximation's accuracy. Interval arithmetic provides a means to ensure that the solution is bounded with absolute certainty.However, whilst interval arithmetic can be applied to any algorithm to ensure bounds on a solution, the limitations of interval arithmetic can lead to bounds that are not always tight and hence not particularly useful. As a result, some algorithms are specifically designed with interval arithmetic in mind to find high quality bounds on a solution; the Krawczyk algorithm is one such algorithm. The Krawczyk algorithm is targeted towards solving systems of linear equations, which is a common problem in scientific computing and has drawn a wide interest in the FPGA community. We show that by accelerating this algorithm in hardware, developing specialised arithmetic units, it is possible to gain orders of magnitude improvement in execution time over a C implementation.

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Section: Introductionmentioning

confidence: 99%

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA

Lann

Boland

Constantinides

2011

Lecture Notes in Computer Science

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“…Moreover, in the comparison to the work in [9] and [12], our design can implement various VP algebraic and transcendental functions in the unified hardware.…”

Section: A Accuracy Of Vv-processormentioning

confidence: 99%

“…The speed of VV-Processor is predicted based on the frequency in Table 2 and the number of cycles in Table 5. Table 5, we compare the performance of our design to two existing design, VPIAP processor [9] and CORDIC processor [12], [17]. The VPIAP processor was designed to perform the basic VP arithmetic operations.…”

Section: A Accuracy Of Vv-processormentioning

confidence: 99%

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FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic

Lei

Dou

Zhou

2011

IEICE Trans. Inf. & Syst.

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SUMMARYMany scientific applications require efficient variableprecision floating-point arithmetic. This paper presents a special-purpose Very Large Instruction Word (VLIW) architecture for variable precision floating-point arithmetic (VV-Processor) on FPGA. The proposed processor uses a unified hardware structure, equipped with multiple custom variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved through the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. We take division and exponential function as examples to illustrate the design of variable-precision elementary algorithms in VV-Processor. Finally, we create a prototype of VV-Processor unit on a Xilinx XC6VLX760-2FF1760 FPGA chip. The experimental results show that one VV-Processor unit, running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 5X-37X for basic variable-precision arithmetic operations and elementary functions.

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“…A limited number of hardware implementations of interval arithmetic can be found in the literature [1,12,13]. A hardware implementation of the CESTAC method has also been published [2].…”

Section: Introductionmentioning

confidence: 99%

A monte-carlo floating-point unit for self-validating arithmetic

Yeung

Young

Leong

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Monte-Carlo arithmetic is a form of self-validating arithmetic that accounts for the effect of rounding errors. We have implemented a floating point unit that can perform either IEEE 754 or Monte-Carlo floating point computation, allowing hardware accelerated validation of results during execution. Experiments show that our approach has a modest hardware overhead and allows the propagation of rounding error to be accurately estimated.

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A family of variable-precision interval arithmetic processors

Cited by 58 publications

References 28 publications

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic

A monte-carlo floating-point unit for self-validating arithmetic

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