A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators

Juracy, Leonardo R.; Amory, Alexandre M.; Moraes, Fernando

doi:10.1109/tcsi.2022.3204932

Cited by 4 publications

(1 citation statement)

References 31 publications

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“…SRAM differs from dynamic random-access memory (DRAM), which must be updated regularly [5,6]. SRAM is both quicker and costlier than DRAM [7,8]; therefore it is often utilized in CPU cache, whereas DRAM is utilized in the main memory of a computer. Cypress is the world leader in Synchronous (Sync) SRAM, with lead times of six weeks or less, 99 percent or greater on-time shipment, and legacy product support lasting up to 20 years, having supplied more than 2.7 billion aggregate units.…”

Section: Introductionmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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Section: Introductionmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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Deploying human activity recognition in embedded RISC-V processors

Nunes,

Reusch,

Luza

et al. 2024

Des Autom Embed Syst

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Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey

Bertazzoni,

Canese,

Cardarilli

et al. 2024

IEEE Access

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This paper proposes a Design Space Exploration for Edge machine learning through the utilization of the novel MathWorks FPGA Deep Learning Processor IP, featured in the HDL Deep Learning toolbox. With the ever-increasing demand for real-time machine learning applications, there is a critical need for efficient and low-latency hardware solutions that can operate at the edge of the network, in close proximity to the data source. The HDL Deep Learning toolbox provides a flexible and customizable platform for deploying deep learning models on FPGAs, enabling effective inference acceleration for embedded IoT applications. In this study, our primary focus lies in investigating the impact of parallel processing elements on the performance and resource utilization of the FPGA-based processor. By analyzing the trade-offs between accuracy, speed, energy efficiency, and hardware resource utilization, we aim to gain valuable insights into making optimal design choices for FPGA-based implementations. Our evaluation is conducted on the AMD-Xilinx ZC706 development board, which serves as the target device for our experiments. We consider all the compatible Convolutional Neural Networks available within the HDL Deep Learning toolbox to comprehensively assess the performances.

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A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators

Cited by 4 publications

References 31 publications

Development of SRAM-APB protocol interface and verification

Development of SRAM-APB protocol interface and verification

Deploying human activity recognition in embedded RISC-V processors

Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey

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