A Fast and Configurable Pattern Matching Hardware Architecture for Intrusion Detection

Liu, Yizhen; Xu, Ding; Dong, Lei; Sun, Lingge

doi:10.1109/wkdd.2009.111

Cited by 3 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Implementing Intrusion Detection Systems on FPGA is a topic that has been more or less discussed in literature. The topic was approached from different angles, since existing algorithms such as Wu-Manber [39] and Aho-Corasik [40], which could be efficient in accelerating rule-matching operations, are applicable to strings. However, the rule sets that intrusion detection systems like Snort use are based on regular expressions (regex).…”

Section: Related Work and Progress Beyond States-of-the-artmentioning

confidence: 99%

“…The authors of [37] claim that their technique led to circuits that are more than twice as dense as other proposed designs, however the throughput necessary for processing at gigabit line speeds and even beyond was maintained. The IDS software versions like Snort use some rule matching algorithms (such as the above-mentioned Wu Manber [39] and Aho-Corasik [40]), which can be implemented on hardware in order to accelerate the detection operations [41]. These algorithms need to be redesigned in order to use regular expressions.…”

Section: Related Work and Progress Beyond States-of-the-artmentioning

confidence: 99%

See 1 more Smart Citation

Towards Accelerating Intrusion Detection Operations at the Edge Network using FPGAs

Rebahi

Catal

Tcholtchev

et al. 2020

2020 Fifth International Conference on Fog and Mobile Edge Computing (FMEC)

View full text Add to dashboard Cite

In the current paper, we present our work towards accelerating intrusion detection operations at the edge network using FPGAs.Cloud computing and network function virtualization have led to a new appealing paradigm for service delivery and management. Unfortunately, this paradigm fails to correctly support IoT applications and services that seek better communication platforms. Security as a Service can also be seen as a cloud-based model that needs to be accommodated to fulfill these services requirements. Again, one of the main issues to be addressed in this context is how to improve the performance of such systems or services in order to make them capable of coping with the huge amount of data while remaining reliable. A potential solution is the FPGA based edge computing, which is a powerful combination offering FPGA acceleration capabilities together with edge and fog benefits. Indeed, our work focusses on devising an Intrusion Prevention architecture called FORTISEC (40SEC), that is meant to operate in a completely softwarized as well as in an FPGA accelerated mode. Thereby, we present suitable algorithms, design methodologies and well defined components towards the implementation of accelerated intrusion prevention on the edge. It is worth to mention that although 40SEC is discussed here in the context of edge computing, it can serve as a security solution for any Small and Medium Enterprise looking for full protection of its network at a reasonable price. We also present a testbed being utilized for the implementation of 40SEC and its performance testing.

show abstract

Section: Related Work and Progress Beyond States-of-the-artmentioning

confidence: 99%

Section: Related Work and Progress Beyond States-of-the-artmentioning

confidence: 99%

Towards Accelerating Intrusion Detection Operations at the Edge Network using FPGAs

Rebahi

Catal

Tcholtchev

et al. 2020

2020 Fifth International Conference on Fog and Mobile Edge Computing (FMEC)

View full text Add to dashboard Cite

show abstract

“…Pattern matching can be performed implementing in hardware different algorithms used by software version of IDSs like Aho-Corasik [17] [14], or WuManber [3]. Moscola [5] proposed a Deterministic Finite Automata(DFA), supporting multi bytes comparisons and partial matches.…”

Section: Related Workmentioning

confidence: 99%

An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections

Greco

Pontarelli

Teofili

2010

2010 VI Southern Programmable Logic Conference (SPL)

View full text Add to dashboard Cite

In this paper a novel architecture for string matching is presented. It is oriented to an FPGA implementation and, differently from other similar works, it is particularly suitable for rules matching in multiple streams. The paper presents our developed architecture able to efficiently manage different streams, discusses how to optimize the design to limit the number of FPGA logic resources and shows the obtained results.

show abstract

A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions

Niemiec

Batista

Schaeffer-Filho

et al. 2020

IEEE Commun. Surv. Tutorials

View full text Add to dashboard Cite

A Fast and Configurable Pattern Matching Hardware Architecture for Intrusion Detection

Cited by 3 publications

References 11 publications

Towards Accelerating Intrusion Detection Operations at the Edge Network using FPGAs

Towards Accelerating Intrusion Detection Operations at the Edge Network using FPGAs

An FPGA based architecture for complex rule matching with stateful inspection of multiple TCP connections

A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions

Contact Info

Product

Resources

About