A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

Abstract

Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load. ARTICLE HISTORY

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

“…The utilization of efficient and energy-saving techniques [18][19][20][21] based on 180 nm technology and subsequent advancements has facilitated the improvement of chip area. Although they possess significant advantages in terms of space and energy, they may not be well suited for applications that require low latency.…”

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

“…This must be fixed if power use is to be optimized. Fast and low power consumption strategies [10,11] have been employed; these designs utilize technology of 90 nm or higher, which is how the area may be increased. In these models, there is a need for further design optimization and improvement.…”

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

“…Most DCCs used in DRAM applications utilize a small-swing to full-swing level shifter (= also known as a CML-to-CMOS level converter) [24,25] to amplify the small-swing clock signal to full-swing CMOS level [1,2,6,13,20,24,25]. Generally, the conventional level shifter has a problem that is very vulnerable to process corner variation.…”

“…Generally, the conventional level shifter has a problem that is very vulnerable to process corner variation. [25] shows that the output duty cycle of the level shifter can be more than 10% distortion. Therefore, DCCs using a level shifter can cause large duty-cycle errors in the presence of process corner variation.…”