A fast and low-power level shifter for multi-supply voltage designs

Abstract

This paper proposes a high-speed and ultra-low power level shifter (LS) capable of realizing wide-range voltage level conversion. Two key features are contained in the presented LS to support its superior performances. First, a novel boost control circuit is proposed to boost input voltage and strengthen pull-down driven capability, which results in significant improvement of operation speed and conversion range. Second, multi-threshold COMS (MTCMOS) and sub-threshold device sizing techniques are employed to reduce the static current, thereby obtaining ultra-low leakage power consumption. Post-layout simulation results demonstrate that the proposed LS implemented with SMIC 55-nm technology can convert 140mV lowvoltage to 1.2V. Meanwhile, when evaluated with the low supply voltage of 0.3V at 1MHz frequency, the transition energy of the presented LS is 87.35 fJ. Moreover, the static power consumption and propagation delay are only 64.2 pW and 18.07ns, respectively.

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

“…In reference [15], two conventional LS architectures are discussed: the current mirroring (CM) and the differential cascading voltage switching (DCVS) models. However, this approach is accompanied by significant power consumption when dealing with highvoltage input signals, hence making it less suitable for low-power devices.…”

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

“…This model has latency and area of 27.08 ns and 47.78 μm 2 respectively. In [7], Current-mirror (CM) and differential cascade voltage switch (DCVS) structures are the two most common forms of traditional LSs. However, when dealing with high supply voltage (VDDH), the CM structure results in considerable static power waste owing to leakage current via the transistors.…”