A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Nakamura, Yūichi; Hosokawa, Kouhei; Kuroda, I.; Yoshikawa, Ko; Yoshimura, Takeshi

doi:10.1145/996566.996655

Cited by 56 publications

(24 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For SystemC simulation, utilizing various parallel simulation techniques [20], [21] on symmetric multiprocessing (SMP) machines can further improve the SystemC simulation performance. For slow HDL simulation, the NetVP can be integrated with an FPGA board to create a hardware/software co-verification environment [22] that uses faster FPGA emulation to replace the HDL simulation.…”

Section: Resultsmentioning

confidence: 99%

A System-Level Network Virtual Platform for IPsec Processor Development

Wang

Chen

2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYDeveloping a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform (NetVP) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.

show abstract

Section: Resultsmentioning

confidence: 99%

A System-Level Network Virtual Platform for IPsec Processor Development

Wang

Chen

2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…While the typical DMA read data rate was found to be 35-40 Mbytes/sec, it has been shown to be faster on other laptops [12], providing an even faster emulation environment. The clock rate for the FPGA circuit was 49 MHz, giving a much faster emulation time than previously reported in [6] and [7], where verification was performed at a maximum rate of 1.1 MHz.…”

Section: Ivresultsmentioning

confidence: 99%

“…To allow for both controllability and observability of the accelerators by the test/emulation engine, the platform allocates four different memory spaces to each hardware slot in a manner extending the work of [6]: The register file memories are for the writing and reading of control signals. The write-only register file can be used for important flags and parameters that are necessary for the processing performed by the hardware slot.…”

Section: Virtual Socket Platformmentioning

confidence: 99%

A software/hardware platform for rapid prototyping of video and multimedia designs

Schumacher¹,

Mattavelli²,

Chirila-Rus³

et al. 2005

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

View full text Add to dashboard Cite

--Traditional design and test of complex multimedia systems involves a large number of test vectors and is a difficult and time-consuming task. The simulation times are prohibitively long on current desktop computers. Driving actual design scenarios and timing burst behavior which produce real-time effects is difficult to do with current simulation environments. This paper describes a rapid emulation framework for accessing multiple hardware IP blocks on an FPGA. This solution involves an abstraction of the FPGA platform by having a virtual socket layer that resides between the design and the test vehicles. A rapid prototyping platform is thus created, and its use with complex video and multimedia systems is described.

show abstract

“…Their primary concern is how to synchronize the emulator with other simulators. Nakamura et al proposed a lock-step based HW/SW coemulation technique based on shared register communication [11]. They should pay heavy synchronization overhead due to too frequent synchronizations.…”

Section: B System Verification With Hardware Emulationmentioning

confidence: 99%

A timed HW/SW coemulation technique for fast yet accurate system verification

Yang

2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

View full text Add to dashboard Cite

-In System-on-chip (SoC) design, it is essential to verify the correctness of design before a chip is fabricated. While conventional hardware emulators validate functional correctness of hardware components quickly, only a few researches exist to use hardware emulators for timing verification since synchronization between the hardware emulator and the other parts easily overwhelms the gain of hardware emulator. In this paper we propose a novel hardware/software coemulation framework for fast yet accurate system verification based on the virtual synchronization technique. For virtual synchronization, interface protocol and interface logic between a hardware emulator and the HW/SW coemulation kernel are proposed. Experiments with real-life examples prove the effectiveness of the proposed technique.

show abstract

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Cited by 56 publications

References 9 publications

A System-Level Network Virtual Platform for IPsec Processor Development

A System-Level Network Virtual Platform for IPsec Processor Development

A software/hardware platform for rapid prototyping of video and multimedia designs

A timed HW/SW coemulation technique for fast yet accurate system verification

Contact Info

Product

Resources

About