A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Abstract

Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.

Optimizing Hill Climbing Algorithm Parameters for Generation of Cryptographically Strong S-Boxes

“…We explore the HC algorithm, which is used to solve various mathematical optimization problems [14][15][16][17]. For example, in [10] there is the pseudocode of one of the versions of the HC algorithm for generating S-boxes (Fig.…”

“…In this article, we propose a Hill-Climbing (HC) [12,13] optimization strategy to fill in this gap. HC is one of the most effective local optimization algorithms (LSA), which is used to solve various AI problems [14][15][16][17].…”

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

“…However, it has quickly become apparent that fault free region is not satisfactory in terms of area size [41]. For this reason, researchers focus on challenges including defect and variance tolerances [40] [28]. In this study, we apply a new fault tolerance technique for four-terminal crossbars (lattices).…”

Integrated Synthesis Methodology for Crossbar Arrays

“…Decision of which crosspoint switches are going to be used during logic design plays a crucial role in performance optimization. To achieve variation tolerant delay values, different optimization algorithms have been proposed [28] [15]. These algorithms aim to optimize the worst-case delay values in logic mapping.…”