A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology

Abstract

A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system's standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz).

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers

“…This is quite suitable for those high performance communication systems such as the frequency-hopping system, because PLL always works and the frequency or the sub-band of VCO changes continually in frequency-hopping system. On the other hand, the proposed AFC circuit is not suitable for low power communication systems, such as biomedical electronic system [30,31]. Because PLL may be turned off frequently for low power design, it requires long time to set up the TOF while PLL power on every time, and the set up time of TOF will be added to calibration time in such situation.…”