A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Abstract

This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μs which is 35 TREF, and core area was 0.291 mm2.

A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader

“…The DPFD is an important part of the ADPLL architecture which determines the difference and mismatch of the phase and frequency of two input signals, namely the frequency reference signal and the divided DCO output frequency signal. The DPFD has been redesigned and restructured by many researchers [12,[22][23][24][25] to achieve fast detection and acquisition performance in ADPLL. The Time-to-Digital Converter (TDC) is a famous design architecture for developing a DPFD.…”

“…A CU is another approach to filter the bit control in the ADPLL instead of using the Digital Loop Filter (DLF). There are many considerations in designing the DLF to achieve fast locking performance, such as by considering a proper loop gain selection for the gain controller [25], a dynamic filter bandwidth adjustment [29,30], a voltage buffer amplifier, etc. and these make the design complex and unstable.…”