A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Yoon, Junsub; Heo, Seo Weon; Kim, Jongsun

doi:10.1587/elex.13.20161020

Cited by 3 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Each CDL includes 15 delay cells 28,29 and is turned on or off by 15 thermometer codes converted from 4 binary codes. The logic function of the CDL can be expressed by Equations ( 2)-( 6):…”

Section: Digitally Controlled Delay Linementioning

confidence: 99%

“…Each CDL includes 15 delay cells 28,29 and is turned on or off by 15 thermometer codes converted from 4 binary codes. The logic function of the CDL can be expressed by Equations (2)–(6):

in 0 < normaln > = ({, \begin{matrix} leftarray \\ array in, n = 0 \\ array out1 < n - 1 >, {n \in N | 1 \leq n \leq 14} \end{matrix})

\begin{matrix} right out 1 < n > = \overset{true‾}{D < n > in 0 < n >}, {n \in N | 0 \leq n \leq 14} \end{matrix}

in 1 < normaln > = ({, \begin{matrix} leftarray \\ array out 0 < n + 1 >, {n \in N | 0 \leq n \leq 13} \\ array out 1 < n >, n = 14 \end{matrix})

\begin{matrix} right out 0 < n > = \overset{true¯}{\overset{true¯}{\overset{true‾}{D < n >} in 0 < n >} in 1 < n >}, {n \in N | 0 \leq n \leq 14} \end{matrix}

out = o...

…”

Section: Transceiver Circuit Designmentioning

confidence: 99%

See 1 more Smart Citation

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

show abstract

Section: Digitally Controlled Delay Linementioning

confidence: 99%

“…Each CDL includes 15 delay cells 28,29 and is turned on or off by 15 thermometer codes converted from 4 binary codes. The logic function of the CDL can be expressed by Equations (2)–(6):

in 0 < normaln > = ({, \begin{matrix} leftarray \\ array in, n = 0 \\ array out1 < n - 1 >, {n \in N | 1 \leq n \leq 14} \end{matrix})

\begin{matrix} right out 1 < n > = \overset{true‾}{D < n > in 0 < n >}, {n \in N | 0 \leq n \leq 14} \end{matrix}

in 1 < normaln > = ({, \begin{matrix} leftarray \\ array out 0 < n + 1 >, {n \in N | 0 \leq n \leq 13} \\ array out 1 < n >, n = 14 \end{matrix})

\begin{matrix} right out 0 < n > = \overset{true¯}{\overset{true¯}{\overset{true‾}{D < n >} in 0 < n >} in 1 < n >}, {n \in N | 0 \leq n \leq 14} \end{matrix}

out = o...

…”

Section: Transceiver Circuit Designmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS). The DCC is also employed as part of a delay-locked loop (DLL) for DDR3/ DDR4 SDRAMs and is mounted at the front or rear end of the DLL circuit [8,10,17,21,22,23].…”

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

show abstract

Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory

Zhu²,

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Cited by 3 publications

References 12 publications

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory

Contact Info

Product

Resources

About