A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Abstract

To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

Categorization and Characterization of Time Domain CMOS Temperature Sensors

“…Lastly, as the temperature estimation function of (2) is a function of not only μ(T) and V TH (T) but also V DD , this temperature sensor is necessarily sensitive to the power supply variation. Thus, this temperature sensor should be implemented along with an additional integrated voltage regulator [ 64 , 65 , 66 , 67 , 68 , 69 , 70 , 71 , 72 , 73 , 74 , 75 ] for constant V DD . The measured V DD sensitivity is as large as 1.6 °C/mV with no voltage regulator.…”

A High-Loop-Gain Low-Dropout Regulator with Adaptive Positive Feedback Compensation Handling 1-A Load Current

“…Wider UGF improves the transient response, usually resulting in larger quiescent current and worse regulation accuracy [27,28]. Digital LDOs can achieve fast transient responses, but the maximum load current is usually small [29,30].…”