A fault-tolerant 176 Gbit solid state mass memory architecture

Cardarilli, G.C.; Marinucci, P.; Ottavi, Marco; Salsano, A.

doi:10.1109/dftvs.2000.887155

Cited by 6 publications

(5 citation statements)

References 5 publications

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“…For a spaceborne equipment, two requirements of reliability have to be satisfied [3,4] : any single failure should be insulated and unable to destruct the whole system; a predetermined probability of survival must be kept during the mission time.…”

Section: Memory Architecture and Reliabilitymentioning

confidence: 99%

“…The use of such components implies some drawbacks such as high cost due to the special technology and small number of produced parts and low performances compared with commercial-off-the-shelf (COTS) components. Moreover, the requirements of short latency time, high throughput and storage capabilities cannot be satisfied by space qualified components and make the choice of COTS mandatory [2,3] . The fault-tolerant mass memory presented in this paper is based on COTS components.…”

mentioning

confidence: 99%

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Fault-tolerant design of spaceborne mass memory system

Zhang

Chang

Gao

et al. 2010

Trans. Tianjin Univ.

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Abstract：A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components. The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure. Error correcting code (ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset. For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/s. In space environment, ECC combined with periodical scrubbing is appropriate and it reduces the word error rate by 5 orders of magnitude with 1% timing overhead and small hardware expenditure. Keywords：fault-tolerant memory architecture; data integrity; parallel Reed-Solomon codec In space environment, electronic devices are exposed to ionizing radiation such as electrons, protons and heavy ions. This results in a permanent loss after the accumulation of radiation and transient effects induced by single particles, such as single event upset (SEU) and single event latch-up (SEL) [1] . Both the single event effects (SEEs) are induced by electron-hole generated in silicon along the track of energetic particles. The total dose radiation effects can be reduced by using suitable shields. On the other hand, the susceptibility of SEE does not change significantly with shielding. As a consequence, only the presence of SEEs is considered in this paper.To deal with these issues, a typical approach is the development of space qualified electronic devices based on special and expensive technology processes. The use of such components implies some drawbacks such as high cost due to the special technology and small number of produced parts and low performances compared with commercial-off-the-shelf (COTS) components. Moreover, the requirements of short latency time, high throughput and storage capabilities cannot be satisfied by space qualified components and make the choice of COTS mandatory [2,3] . The fault-tolerant mass memory presented in this paper is based on COTS components.

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Section: Memory Architecture and Reliabilitymentioning

confidence: 99%

mentioning

confidence: 99%

Fault-tolerant design of spaceborne mass memory system

Zhang

Chang

Gao

et al. 2010

Trans. Tianjin Univ.

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“…During the latency period the noise corrupts the integrity of data. If the noise is generated by SEU, the BER depends on the latency time of data and it is given by (5) where is the rate of occurrence of SEU and depends on radiation environment and device technologies [29]. 5The correction device performs the error correction function as the inverse operation of noise source.…”

Section: B Data Integrity Evaluationmentioning

confidence: 99%

“…The SSMM presented in this paper is based on COTS components. In the proposed architecture a number of SpaceWire data links [4] access the memory banks through a cross-point switch matrix [5]. This solution is convenient with respect to a bus based architecture in terms of bandwidth, latency and reconfiguration capability.…”

mentioning

confidence: 99%

Fault tolerant solid state mass memory for space applications

Cardarilli

Ottavi

Pontarelli

et al. 2005

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper describes a novel architecture of fault tolerant Solid State Mass Memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of Commercial Off The Shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies [1], [2]. In the proposed architecture error-correcting codes are used to strengthen the commercial Dynamic Random Access Memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. This paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link Interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM.The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

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“…The maximum is obtained for a fully connected graph including the loopback on the nodes. In this case, we have m sequences generated by each node, therefore the number of sequences is m 2 . If the graph has nodes that are not checkpoints, one sequence must be added to the sum.…”

Section: -1 <= S <= M 2 + (N-m)mentioning

confidence: 99%