A fault-tolerant ICAP controller with a selective-area soft error mitigation engine

Adetomi, Adewale; Enemali, Godwin; Arslan, Tughrul

doi:10.1109/ahs.2017.8046378

Cited by 8 publications

(15 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…which are not present in [27] and vice versa. For example, the [39] has decoupling functionalities not reported in [27], while the [27] has bitstream relocation feature and capacity to handle encrypted bitstreams not present in the [39]. Nevertheless, most of operations surrounding dynamic loading of partial bitstreams are reported in both.…”

Section: Creating Partial Reconfiguration Bitstreamsmentioning

confidence: 85%

“…The communication mechanism is necessary to support the generic placement techniques presented in this thesis. In addition, he also designed and implemented a configuration controller which is used both for configuring tasks on the FPGA after placement decisions and also for soft error mitigation techniques [27]. However, the reverse engineering experiments carried out as part of this thesis were used in the design and implementation of the configuration controller.…”

Section: Summary Of Novelty and Contributionmentioning

confidence: 99%

“…However, error classification can be used to improve the performance while some implementations also restrict the scanning to certain parts of the chip containing user designs and hence improves on the average speed of error detection [27].…”

Section: Reliability Issues In Fpgasmentioning

confidence: 99%

See 2 more Smart Citations

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Adetomi

Enemali

Iturbe

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

Self Cite

View full text Add to dashboard Cite

Section: Creating Partial Reconfiguration Bitstreamsmentioning

confidence: 85%

Section: Summary Of Novelty and Contributionmentioning

confidence: 99%

See 1 more Smart Citation

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Adetomi

Enemali

Iturbe

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

Self Cite

View full text Add to dashboard Cite

“…Many researchers have proposed different techniques to manage soft errors in FPGAs. [10][11][12][13][14][15] Adewale Adetomi et al [10], designed ICAP Controller with a selective-area soft error Mitigation Engine. They tried to scan selective-area of the FPGA instead of entire device which saved them the time available for reconfiguration.…”

Section: Previous Related Workmentioning

confidence: 99%

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

S¹,

Dinesha²,

Shashikala³

et al. 2020

IJCNIS

View full text Add to dashboard Cite

Designing a reliable system on reconfigurable devices has become a significant factor for implementing mission critical applications like communication protocols, automotive, nuclear reactor control, and remote applications. With the improvement in fabrication technology, logic density of the field programmable gate arrays has increased rapidly. Because of decrease in feature size, integrated circuits are becoming vulnerable to errors and also the ageing component results in run time faults. FPGAs when used in harsh conditions like high radiation and temperatures, there is a possibility of getting affected by transient faults or the soft errors. In digital communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Reliable design techniques are very much necessary for maintaining the system's normal function. Many of the available techniques are based on redundancy logic causing area overhead for the design. Through this paper, an implementation is illustrated for managing soft errors or the single event upsets. Proposed methodology identifies and avoids the errors occurring at the logic resources where the encryption algorithms are mapped on the device. Thus encryption algorithms work normally without getting affected by the errors. During the simulation process, errors are injected at the configuration memory frames and monitored using a Single event-upset manager (SEM) controller. The proposed design is implemented on Zedboard using Xilinx Vivado 2017.4.

show abstract

“…It is also worth noting that practical relocation techniques require access to the configuration memory of the FPGA, as well as a means of communication between a relocated module and other parts of the chip. Thus, a selfreconfiguration controller [14] with the required access to the configuration memory was instantiated. The controller is used for configuring the chip, as well as copying of data between block memories of the relocation module and the relocated module via the configuration layer.…”

Section: B Relocation Modulementioning

confidence: 99%

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Enemali

Adetomi

Seetharaman

et al. 2018

IEEE Trans. Circuits Syst. II

Self Cite

View full text Add to dashboard Cite

Abstract-Runtime Relocation of circuits on FPGAs have beenproposed for achieving many desirable features including fault tolerance, defragmentation and system load balancing. However, the changes in the architectural composition of FPGAs has made relocation more challenging mainly because FPGAs have become more heterogeneous. Previous and state-of-the-art circuit relocation systems on FPGAs have relied only on direct bitstream relocation which requires the source and destination resource layouts to be the same, as well as access to the design bitstream for manipulation. Hence, their efficiency on modern heterogeneous chips greatly reduces, and mostly cannot be applied to encrypted bitstreams of intellectual property (IP) blocks. In this paper, we present a circuit relocator which augments direct bitstream relocation with a functionalitybased relocation scheme. We demonstrate the feasibility of the proposed technique using a CORDIC application and show that an average of over 2.6-fold increase in number of relocations can be obtained compared to only direct bitstream relocation at expense of a small memory overhead and manageable relocation time for this case study.

show abstract

A fault-tolerant ICAP controller with a selective-area soft error mitigation engine

Cited by 8 publications

References 8 publications

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs

Contact Info

Product

Resources

About