A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip

Pham, Hung-Manh; Pillement, Sébastien; Demigny, Didier

doi:10.1109/reconfig.2009.47

Cited by 13 publications

(4 citation statements)

References 5 publications

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“…An alternative approach is presented in [139], where the complete processor is treated as a functional unit and implemented as a PRM; the method supports scrubbing, as well as a form of relocation referred to as tiling, whereby multiple versions of the same PRM targeting the same PRR but with different spatial distributions are implemented and used. An approach to fault tolerance in multi-processor systems is presented in [140,141].…”

Section: Fault Mitigation Using Both Scrubbing and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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Section: Fault Mitigation Using Both Scrubbing and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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“…The main benefit of this method is that the recovery process can be performed on the fly and the overhead of the synchronization is only the time required to store and restore the processor's state context. The same method is used in [12] for FT architecture with multiprocessors configured into an FPGA.…”

Section: Synchronizationmentioning

confidence: 99%

Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Szurman¹,

Mičulka

Kotásek

2014

2014 9th International Conference on Computer Engineering &Amp; Systems (ICCES)

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Modern fault tolerant systems implemented into FPGAs integrate very often hardware redundancy together with fault tolerant approaches based on active fault recovery and the system reconfiguration. Space and safety-critical applications are examples of systems where the principles of fault tolerance and recovery techniques have increasing importance. Except of fault-masking behavior and FPGA partial reconfiguration, also the synchronization of reconfigured circuit copy with remaining circuits which are during the recovery process still operating,is an integral part of the recovery process in these systems.The synchronization process is closely related to the system architecture, specific requirements and functionality. Our aim is to propose specific methodology to design and implement the most suitable synchronization procedure for the recovery of target fault tolerant system. In this paper, basic principles of our synchronization methodology are described together with generic architecture for synchronization in fault tolerant systems, which was designed for reconfigurable fault tolerant CAN bus control system. This system and performed experiments are in the paper described as well.

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“…Each FPGA contain a fault-tolerant dynamic multi-processors system, consisting of several MicroBlaze (Figure 16). Further details about this system architecture, called FT-DyMPSoC, as well as the fault-tolerance schemes implemented can be found in (Pham et al, 2009) and (Pham et al, 2010) for interested readers. On the overall system, each FPGA is interfaced with a memory that can be accessed by all the processors inside the same FPGA.…”

Section: Fig 14 View Of the Virtex5 5vsx50t Captured From Xilinx Plmentioning

confidence: 99%

“…The Intra-FPGA level corresponds to the fault-tolerance strategy inside each FPGA, and is related to the design of the FT-DyMPSoC system. The fault-mitigation strategy is realized using the connection matrices algorithm (Pham, 2009), and fault are mitigated by using dynamic reconfiguration at the processors level. The second level called Inter-FPGA level corresponds to the overall system presented in Figure 15.…”

Section: Fig 14 View Of the Virtex5 5vsx50t Captured From Xilinx Plmentioning

confidence: 99%

Experiments of In-Vehicle Power Line Communications

Nouvel¹,

Tanguy²,

Pillement³

et al. 2011

Advances in Vehicular Networking Technologies

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A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip

Cited by 13 publications

References 5 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Towards a state synchronization methodology for recovery process after partial reconfiguration of fault tolerant systems

Experiments of In-Vehicle Power Line Communications

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