A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design

H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate the performance of such application-specific multi-core systems effectively, a method based on the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP ) is given, and experiments show that it can effectively simulate the system in a short time and more importantly, it can be used to help analyze the efficiency of each task-parallelization strategy. After optimization, the speedup ratio for each slice decoding can get about 3.06 on average under 4-core multi-core systems.

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An efficient methodology for transaction-level design of multi-core h.264 video decoder

Xia

Qiao

Yang

et al. 2011

2011 IEEE International Conference on Consumer Electronics (ICCE)

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Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications

Kokila¹,

Ramasubramanian²,

Thamma³

2018

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A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design

Cited by 2 publications

References 18 publications

An efficient methodology for transaction-level design of multi-core h.264 video decoder

An efficient methodology for transaction-level design of multi-core h.264 video decoder

Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications

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