2019
DOI: 10.1109/jxcdc.2019.2930222
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A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method

Abstract: In recent years, several designs that use in-memory processing to accelerate machinelearning inference problems have been proposed. Such designs are also a perfect fit for discrete, dynamic, and distributed systems that can solve large-dimensional optimization problems using iterative algorithms. For in-memory computations, ferroelectric field-effect transistors (FerroFETs) owing to their compact area and distinguishable multiple states offer promising possibilities. We present a distributed architecture that … Show more

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Cited by 7 publications
(4 citation statements)
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“…The second approach, i.e. performing a logic operation within one FeFET, was pursued for simple logic gates [192], for ternary content addressable memory [198,199] where one cell utilizes XOR logic, for half and full adder circuits [200] as well as for vector-matrix-multipliers (VMM) [201,202]. The FeFET-based VMMs are a basic element of, for example, deep neural networks [201], and have been additionally exploited for optimizations via the least-squares minimization [202].…”
Section: In-memory Computingmentioning
confidence: 99%
See 1 more Smart Citation
“…The second approach, i.e. performing a logic operation within one FeFET, was pursued for simple logic gates [192], for ternary content addressable memory [198,199] where one cell utilizes XOR logic, for half and full adder circuits [200] as well as for vector-matrix-multipliers (VMM) [201,202]. The FeFET-based VMMs are a basic element of, for example, deep neural networks [201], and have been additionally exploited for optimizations via the least-squares minimization [202].…”
Section: In-memory Computingmentioning
confidence: 99%
“…performing a logic operation within one FeFET, was pursued for simple logic gates [192], for ternary content addressable memory [198,199] where one cell utilizes XOR logic, for half and full adder circuits [200] as well as for vector-matrix-multipliers (VMM) [201,202]. The FeFET-based VMMs are a basic element of, for example, deep neural networks [201], and have been additionally exploited for optimizations via the least-squares minimization [202]. In general, computations within the memory array are very flexible in terms of possible logic operations because the logic functionality is determined by the number of utilized FeFETs and their stored states, not by the array periphery.…”
Section: In-memory Computingmentioning
confidence: 99%
“…Although ferroelectric-transistor-based NNs are expected to show high energy efficiency and several NN array structures exhibit promising characteristics, several specific issues should be investigated from the array perspective. [172][173][174][175] First, the high capacitance between word lines can increase the energy consumption. Additionally, the interference and disturbance characteristics can cause inaccurate NN training and thus should be rigorously investigated.…”
Section: Ferroelectric Transistor Arrays For Nnsmentioning
confidence: 99%
“…This design concept was further applied to RRAM [10,11] and PCM [12] based on redesigned writing and peripheral circuit blocks. Significant potential for using the IMC approach for emerging device-based NVMs was demonstrated by processing the in-FeFET cells with an intrinsic compact area and distinguishable multiple states [13,14]. As a demonstration of PCM, dual-mode double-density PCM based on a novel stressing-mode storage scheme was studied in [15].…”
Section: Bit-cell Level Attemptmentioning
confidence: 99%