A field programmable system chip which combines FPGA and ASIC circuitry

Andrew, W.B.; Carl, G.; Charath, R.K.; Hoff, J.; Modo, R.; Nguyen, Hung K.; Smith, W. J. Bernhard; Rhein, Dietrich; Schulingkamp, J.; Spivak, C.; Steward, J.; Subramaniam, Anand Bala

doi:10.1109/cicc.1999.777270

Cited by 6 publications

(2 citation statements)

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“…Recently, reconfigurable computing is gaining renewed interests from a system LSI design perspective [6]. This is because a reconfigurable computing IP core, that changes its configuration to suit the application, can fill a wide gap between programmable and hardwired IP cores.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI

Yamashina

Motomura

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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This paper first outlines a broad range of reconfigurable computing research activities from a perspective of system LSI designs. Then, the paper focuses onto dynamically reconfigurable logic (DRL) LSI, a prototype chip that we developed to evaluate the reconfigurable computing concept. Through its ability to exchange hardware contexts quickly, this chip can accelerate media/communication applications with customized hardware configurations, yet maintaining scalability towards varying application sizes.

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Section: Introductionmentioning

confidence: 99%

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI

Yamashina

Motomura

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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“…The use of FPGAs has become popular as a way of integrating programmable cores into System on a Chip (SoC) designs [1]. The main advantage of this consists in using configurable logical blocks such as the FPGA, which allows for spatial mapping of algorithms instead of the temporal mapping used in most microprocessor (µP) based systems.…”

Section: Introductionmentioning

confidence: 99%

Distributed processing network architecture for reconfigurable computing

Vallina

Oruklu

Saniie

2005 IEEE International Conference on Electro Information Technology

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This paper introduces a set of rules and guidelines for the implementation of a Distributed Processing Network (DPN) as the basis for a dynamic reconfigurable architecture targeted at improving the performance of microprocessor (µP) based systems in computationally intensive application domains. In order to provide the computation gains needed to improve upon the performance of the µP, the DPN architecture offers: 1) A low reconfiguration overhead, 2) A simple control interface, 3) Dynamic resource allocation, 4) Concurrent execution with dynamic reconfiguration, 5) Lower power dissipation than a µP executing the same computation kernel and, 6) Scalability to tackle tasks of varying resource requirements. DPN is currently targeted at realtime computationally intensive application domains such as compression, and signal transformations.

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Bus architecture of a system on a chip with user-configurable system logic

Winegarden

2000

IEEE J. Solid-State Circuits

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A field programmable system chip which combines FPGA and ASIC circuitry

Abstract: The industry's first combination of FPGA and ASIC technologies is discussed in this paper.

Cited by 6 publications

References 0 publications

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI

Distributed processing network architecture for reconfigurable computing

Bus architecture of a system on a chip with user-configurable system logic

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