A fill-unit approach to multiple instruction issue

Abstract

Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility as in superscalars and the absence of complex dependency-checking logic from the decoder as in VLIW. In this design, a stream of scalar instructions is executed by the hardware and is simultaneously compacted into VLIW-type instructions, which are then stored in a structure called a shadow cache. When a shadow cache line contains the instructions requested by the fetch unit, the scalar instruction stream is preempted and all operations in the shadow cache line are simultaneously issued and executed. The mechanism that compacts instructions is called a ll unit, and was rst proposed for dynamically compacting microoperations into large executable units by Melvin, Shebanow, and Patt in 1988. We have extended their approach to directly handle data dependencies, delayed branches, and speculative execution (using branch prediction). This approach is evaluated using the MIPS architecture, and a sixfunctional-unit machine is found to be 52 to 108% faster than a single-issue processor for unrecompiled SPECint92 benchmarks.

Parallelism in the front-end

“…Many enhancements to these mechanisms have been proposed [9,10,15,19,22], but each of these inherits some problems from the sequential fetch mechanism upon which it is based.…”

Dynamically Scheduling VLIW Instructions

“…In addition, it requires dynamic scheduling hardware in the main data path of the machine, which can have a negative effect on the clock cycle time. Franklin and Smotherman [13] proposed the use of a fill unit [25] to compact a dynamic stream of scalar instructions. Their fill unit accepts decoded instructions from the machine decoder, compacts them into a long instruction (the term used in the rest of this paper to refer to VLIW instructions), and saves this into a shadow cache.…”

“…Nair and Hopkins [26] suggested a VLIW-based machine organization named DIF (dynamic instruction formatting), which also follows the Franklin and Smotherman proposal [13]. The DIF machine incorporates two engines: the VLIW engine and the primary engine.…”

Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences

“…The renaming mechanism requires a fairly large (for example, 512 registers) microoperations register file. Recording of dynamic instruction issue order to achieve VLIW-like issue has been proposed in [Fra94a].…”